Introduce Airoha AN7583 SoC compatible in mediatek PCIe controller
binding.
Similar to GEN3, the Airoha AN7583 GEN2 PCIe controller require the
PBUS csr property to permit the correct functionality of the PCIe
controller.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
.../bindings/pci/mediatek-pcie.yaml | 110 ++++++++++++++++++
1 file changed, 110 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml
index fca6cb20d18b..b91b13a0220c 100644
--- a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml
@@ -13,6 +13,7 @@ properties:
compatible:
oneOf:
- enum:
+ - airoha,an7583-pcie
- mediatek,mt2712-pcie
- mediatek,mt7622-pcie
- mediatek,mt7629-pcie
@@ -55,6 +56,17 @@ properties:
power-domains:
maxItems: 1
+ mediatek,pbus-csr:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to pbus-csr syscon
+ - description: offset of pbus-csr base address register
+ - description: offset of pbus-csr base address mask register
+ description:
+ Phandle with two arguments to the syscon node used to detect if
+ a given address is accessible on PCIe controller.
+
'#interrupt-cells':
const: 1
@@ -90,6 +102,45 @@ required:
allOf:
- $ref: /schemas/pci/pci-host-bridge.yaml#
+ - if:
+ properties:
+ compatible:
+ const: airoha,an7583-pcie
+ then:
+ properties:
+ reg:
+ maxItems: 1
+
+ reg-names:
+ const: port1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: sys_ck1
+
+ reset:
+ maxItems: 1
+
+ reset-names:
+ const: pcie-rst1
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ const: pcie-phy1
+
+ power-domain: false
+
+ required:
+ - resets
+ - reset-names
+ - phys
+ - phy-names
+ - mediatek,pbus-csr
+
- if:
properties:
compatible:
@@ -106,6 +157,8 @@ allOf:
power-domains: false
+ mediatek,pbus-csr: false
+
required:
- phys
- phy-names
@@ -123,6 +176,8 @@ allOf:
phy-names: false
+ mediatek,pbus-csr: false
+
required:
- power-domains
@@ -135,6 +190,8 @@ allOf:
clocks:
minItems: 6
+ mediatek,pbus-csr: false
+
required:
- power-domains
@@ -157,6 +214,8 @@ allOf:
power-domain: false
+ mediatek,pbus-csr: false
+
unevaluatedProperties: false
examples:
@@ -316,3 +375,54 @@ examples:
};
};
};
+
+ # AN7583
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/en7523-clk.h>
+
+ soc_3 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@1fa92000 {
+ compatible = "airoha,an7583-pcie";
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ reg = <0x0 0x1fa92000 0x0 0x1670>;
+ reg-names = "port1";
+
+ clocks = <&scuclk EN7523_CLK_PCIE>;
+ clock-names = "sys_ck1";
+
+ phys = <&pciephy>;
+ phy-names = "pcie-phy1";
+
+ ranges = <0x02000000 0 0x24000000 0x0 0x24000000 0 0x4000000>;
+
+ resets = <&scuclk>; /* AN7583_PCIE1_RST */
+ reset-names = "pcie-rst1";
+
+ mediatek,pbus-csr = <&pbus_csr 0x8 0xc>;
+
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pcie_irq";
+ bus-range = <0x00 0xff>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ <0 0 0 2 &pcie_intc1 1>,
+ <0 0 0 3 &pcie_intc1 2>,
+ <0 0 0 4 &pcie_intc1 3>;
+
+ pcie_intc1_4: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
--
2.51.0On Mon, Sep 29, 2025 at 01:38:02PM +0200, Christian Marangi wrote:
> Introduce Airoha AN7583 SoC compatible in mediatek PCIe controller
> binding.
>
> Similar to GEN3, the Airoha AN7583 GEN2 PCIe controller require the
> PBUS csr property to permit the correct functionality of the PCIe
> controller.
I guess I didn't get my point across before. Test your crap before
sending or I'm going to stop reviewing your stuff.
>
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> ---
> .../bindings/pci/mediatek-pcie.yaml | 110 ++++++++++++++++++
> 1 file changed, 110 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml
> index fca6cb20d18b..b91b13a0220c 100644
> --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml
> @@ -13,6 +13,7 @@ properties:
> compatible:
> oneOf:
> - enum:
> + - airoha,an7583-pcie
> - mediatek,mt2712-pcie
> - mediatek,mt7622-pcie
> - mediatek,mt7629-pcie
> @@ -55,6 +56,17 @@ properties:
> power-domains:
> maxItems: 1
>
> + mediatek,pbus-csr:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + - items:
> + - description: phandle to pbus-csr syscon
> + - description: offset of pbus-csr base address register
> + - description: offset of pbus-csr base address mask register
> + description:
> + Phandle with two arguments to the syscon node used to detect if
> + a given address is accessible on PCIe controller.
> +
> '#interrupt-cells':
> const: 1
>
> @@ -90,6 +102,45 @@ required:
> allOf:
> - $ref: /schemas/pci/pci-host-bridge.yaml#
>
> + - if:
> + properties:
> + compatible:
> + const: airoha,an7583-pcie
> + then:
> + properties:
> + reg:
> + maxItems: 1
That's already the maximum. Drop.
> +
> + reg-names:
> + const: port1
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + const: sys_ck1
> +
> + reset:
> + maxItems: 1
That's already the maximum. Drop.
> +
> + reset-names:
> + const: pcie-rst1
> +
> + phys:
> + maxItems: 1
That's already the maximum. Drop.
> +
> + phy-names:
> + const: pcie-phy1
> +
> + power-domain: false
> +
> + required:
> + - resets
> + - reset-names
> + - phys
> + - phy-names
> + - mediatek,pbus-csr
> +
> - if:
> properties:
> compatible:
> @@ -106,6 +157,8 @@ allOf:
>
> power-domains: false
>
> + mediatek,pbus-csr: false
> +
> required:
> - phys
> - phy-names
> @@ -123,6 +176,8 @@ allOf:
>
> phy-names: false
>
> + mediatek,pbus-csr: false
> +
> required:
> - power-domains
>
> @@ -135,6 +190,8 @@ allOf:
> clocks:
> minItems: 6
>
> + mediatek,pbus-csr: false
> +
> required:
> - power-domains
>
> @@ -157,6 +214,8 @@ allOf:
>
> power-domain: false
>
> + mediatek,pbus-csr: false
> +
> unevaluatedProperties: false
>
> examples:
> @@ -316,3 +375,54 @@ examples:
> };
> };
> };
> +
> + # AN7583
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/en7523-clk.h>
> +
> + soc_3 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + pcie@1fa92000 {
> + compatible = "airoha,an7583-pcie";
> + device_type = "pci";
> + linux,pci-domain = <1>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + reg = <0x0 0x1fa92000 0x0 0x1670>;
> + reg-names = "port1";
> +
> + clocks = <&scuclk EN7523_CLK_PCIE>;
> + clock-names = "sys_ck1";
> +
> + phys = <&pciephy>;
> + phy-names = "pcie-phy1";
> +
> + ranges = <0x02000000 0 0x24000000 0x0 0x24000000 0 0x4000000>;
> +
> + resets = <&scuclk>; /* AN7583_PCIE1_RST */
> + reset-names = "pcie-rst1";
> +
> + mediatek,pbus-csr = <&pbus_csr 0x8 0xc>;
> +
> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "pcie_irq";
> + bus-range = <0x00 0xff>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &pcie_intc1 0>,
> + <0 0 0 2 &pcie_intc1 1>,
> + <0 0 0 3 &pcie_intc1 2>,
> + <0 0 0 4 &pcie_intc1 3>;
> +
> + pcie_intc1_4: interrupt-controller {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + };
> + };
> + };
> --
> 2.51.0
>
On Mon, 29 Sep 2025 13:38:02 +0200, Christian Marangi wrote:
> Introduce Airoha AN7583 SoC compatible in mediatek PCIe controller
> binding.
>
> Similar to GEN3, the Airoha AN7583 GEN2 PCIe controller require the
> PBUS csr property to permit the correct functionality of the PCIe
> controller.
>
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> ---
> .../bindings/pci/mediatek-pcie.yaml | 110 ++++++++++++++++++
> 1 file changed, 110 insertions(+)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/mediatek-pcie.example.dtb: pcie@1fa92000 (airoha,an7583-pcie): Unevaluated properties are not allowed ('resets' was unexpected)
from schema $id: http://devicetree.org/schemas/pci/mediatek-pcie.yaml#
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250929113806.2484-4-ansuelsmth@gmail.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
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