Add device tree nodes for the mdss1 DPTX0 and DPTX1 controllers
with their corresponding PHYs.
Signed-off-by: Mani Chandana Ballary Kuntumalla <quic_mkuntuma@quicinc.com>
---
arch/arm64/boot/dts/qcom/lemans.dtsi | 245 +++++++++++++++++++++++++++
1 file changed, 245 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index a78daa827fcd..4af9a439d68f 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -6839,6 +6839,27 @@ mdss1_mdp: display-controller@22001000 {
interrupt-parent = <&mdss1>;
interrupts = <0>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dpu1_intf0_out: endpoint {
+ remote-endpoint = <&mdss1_dp0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ dpu1_intf4_out: endpoint {
+ remote-endpoint = <&mdss1_dp1_in>;
+ };
+ };
+ };
+
mdss1_mdp_opp_table: opp-table {
compatible = "operating-points-v2";
@@ -6863,6 +6884,228 @@ opp-650000000 {
};
};
};
+
+ mdss1_dp0_phy: phy@220c2a00 {
+ compatible = "qcom,sa8775p-edp-phy";
+
+ reg = <0x0 0x220c2a00 0x0 0x200>,
+ <0x0 0x220c2200 0x0 0xd0>,
+ <0x0 0x220c2600 0x0 0xd0>,
+ <0x0 0x220c2000 0x0 0x1c8>;
+
+ clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "aux",
+ "cfg_ahb";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ mdss1_dp1_phy: phy@220c5a00 {
+ compatible = "qcom,sa8775p-edp-phy";
+
+ reg = <0x0 0x220c5a00 0x0 0x200>,
+ <0x0 0x220c5200 0x0 0xd0>,
+ <0x0 0x220c5600 0x0 0xd0>,
+ <0x0 0x220c5000 0x0 0x1c8>;
+
+ clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "aux",
+ "cfg_ahb";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ mdss1_dp0: displayport-controller@22154000 {
+ compatible = "qcom,sa8775p-dp";
+
+ reg = <0x0 0x22154000 0x0 0x104>,
+ <0x0 0x22154200 0x0 0x0c0>,
+ <0x0 0x22155000 0x0 0x770>,
+ <0x0 0x22156000 0x0 0x09c>,
+ <0x0 0x22157000 0x0 0x09c>,
+ <0x0 0x22158000 0x0 0x09c>,
+ <0x0 0x22159000 0x0 0x09c>,
+ <0x0 0x2215a000 0x0 0x23c>,
+ <0x0 0x2215b000 0x0 0x23c>;
+
+ interrupt-parent = <&mdss1>;
+ interrupts = <12>;
+
+ clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel",
+ "stream_1_pixel",
+ "stream_2_pixel",
+ "stream_3_pixel";
+ assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>;
+ assigned-clock-parents = <&mdss1_dp0_phy 0>,
+ <&mdss1_dp0_phy 1>,
+ <&mdss1_dp0_phy 1>,
+ <&mdss1_dp0_phy 1>,
+ <&mdss1_dp0_phy 1>;
+ phys = <&mdss1_dp0_phy>;
+ phy-names = "dp";
+
+ operating-points-v2 = <&mdss1_dp_opp_table>;
+ power-domains = <&rpmhpd SA8775P_MMCX>;
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss1_dp0_in: endpoint {
+ remote-endpoint = <&dpu1_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss1_dp0_out: endpoint { };
+ };
+ };
+
+ mdss1_dp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ mdss1_dp1: displayport-controller@2215c000 {
+ compatible = "qcom,sa8775p-dp";
+
+ reg = <0x0 0x2215c000 0x0 0x104>,
+ <0x0 0x2215c200 0x0 0x0c0>,
+ <0x0 0x2215d000 0x0 0x770>,
+ <0x0 0x2215e000 0x0 0x09c>,
+ <0x0 0x2215f000 0x0 0x09c>,
+ <0x0 0x22160000 0x0 0x09c>,
+ <0x0 0x22161000 0x0 0x09c>,
+ <0x0 0x22162000 0x0 0x23c>,
+ <0x0 0x22163000 0x0 0x23c>;
+
+ interrupt-parent = <&mdss1>;
+ interrupts = <13>;
+
+ clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel",
+ "stream_1_pixel";
+ assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
+ <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
+ assigned-clock-parents = <&mdss1_dp1_phy 0>,
+ <&mdss1_dp1_phy 1>,
+ <&mdss1_dp1_phy 1>;
+ phys = <&mdss1_dp1_phy>;
+ phy-names = "dp";
+
+ operating-points-v2 = <&mdss1_dp1_opp_table>;
+ power-domains = <&rpmhpd SA8775P_MMCX>;
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss1_dp1_in: endpoint {
+ remote-endpoint = <&dpu1_intf4_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss1_dp1_out: endpoint { };
+ };
+ };
+
+ mdss1_dp1_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
};
dispcc1: clock-controller@22100000 {
@@ -6872,6 +7115,8 @@ dispcc1: clock-controller@22100000 {
<&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>,
+ <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>,
+ <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>,
<0>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>;
power-domains = <&rpmhpd SA8775P_MMCX>;
--
2.34.1On 9/26/25 10:59 AM, Mani Chandana Ballary Kuntumalla wrote:
> Add device tree nodes for the mdss1 DPTX0 and DPTX1 controllers
> with their corresponding PHYs.
>
> Signed-off-by: Mani Chandana Ballary Kuntumalla <quic_mkuntuma@quicinc.com>
> ---
[...]
> + mdss1_dp0: displayport-controller@22154000 {
> + compatible = "qcom,sa8775p-dp";
> +
> + reg = <0x0 0x22154000 0x0 0x104>,
sz = 0x200
> + <0x0 0x22154200 0x0 0x0c0>,
sz = 0x200
> + <0x0 0x22155000 0x0 0x770>,
sz = 0xc00> + <0x0 0x22156000 0x0 0x09c>,
> + <0x0 0x22157000 0x0 0x09c>,
> + <0x0 0x22158000 0x0 0x09c>,
> + <0x0 0x22159000 0x0 0x09c>,
sz = 0x400 for all 0x9c
> + <0x0 0x2215a000 0x0 0x23c>,
> + <0x0 0x2215b000 0x0 0x23c>;
0x23c -> 0x600
[...]
> + mdss1_dp1: displayport-controller@2215c000 {
> + compatible = "qcom,sa8775p-dp";
> +
> + reg = <0x0 0x2215c000 0x0 0x104>,
> + <0x0 0x2215c200 0x0 0x0c0>,
> + <0x0 0x2215d000 0x0 0x770>,
> + <0x0 0x2215e000 0x0 0x09c>,
> + <0x0 0x2215f000 0x0 0x09c>,
> + <0x0 0x22160000 0x0 0x09c>,
> + <0x0 0x22161000 0x0 0x09c>,
> + <0x0 0x22162000 0x0 0x23c>,
> + <0x0 0x22163000 0x0 0x23c>;
0x2216_2000 and _3000 don't exist, there's no MST2/3
sizes should be changed similarly
[...]
> dispcc1: clock-controller@22100000 {
> @@ -6872,6 +7115,8 @@ dispcc1: clock-controller@22100000 {
> <&rpmhcc RPMH_CXO_CLK>,
> <&rpmhcc RPMH_CXO_CLK_A>,
> <&sleep_clk>,
> + <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>,
> + <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>,
> <0>, <0>, <0>, <0>,
You need to remove the same amount of zeroes that you added
Konrad
> <0>, <0>, <0>, <0>;
> power-domains = <&rpmhpd SA8775P_MMCX>;
On 10/8/2025 6:10 PM, Konrad Dybcio wrote:
> On 9/26/25 10:59 AM, Mani Chandana Ballary Kuntumalla wrote:
>> Add device tree nodes for the mdss1 DPTX0 and DPTX1 controllers
>> with their corresponding PHYs.
>>
>> Signed-off-by: Mani Chandana Ballary Kuntumalla <quic_mkuntuma@quicinc.com>
>> ---
>
> [...]
>
>> + mdss1_dp0: displayport-controller@22154000 {
>> + compatible = "qcom,sa8775p-dp";
>> +
>> + reg = <0x0 0x22154000 0x0 0x104>,
>
> sz = 0x200
>
>> + <0x0 0x22154200 0x0 0x0c0>,
>
> sz = 0x200
>
>> + <0x0 0x22155000 0x0 0x770>,
>
> sz = 0xc00> + <0x0 0x22156000 0x0 0x09c>,
>> + <0x0 0x22157000 0x0 0x09c>,
>> + <0x0 0x22158000 0x0 0x09c>,
>> + <0x0 0x22159000 0x0 0x09c>,
>
> sz = 0x400 for all 0x9c
>
>> + <0x0 0x2215a000 0x0 0x23c>,
>> + <0x0 0x2215b000 0x0 0x23c>;
>
> 0x23c -> 0x600
>
> [...]
>
>
>> + mdss1_dp1: displayport-controller@2215c000 {
>> + compatible = "qcom,sa8775p-dp";
>> +
>> + reg = <0x0 0x2215c000 0x0 0x104>,
>> + <0x0 0x2215c200 0x0 0x0c0>,
>> + <0x0 0x2215d000 0x0 0x770>,
>> + <0x0 0x2215e000 0x0 0x09c>,
>> + <0x0 0x2215f000 0x0 0x09c>,
>> + <0x0 0x22160000 0x0 0x09c>,
>> + <0x0 0x22161000 0x0 0x09c>,
>> + <0x0 0x22162000 0x0 0x23c>,
>> + <0x0 0x22163000 0x0 0x23c>;
>
> 0x2216_2000 and _3000 don't exist, there's no MST2/3
>
> sizes should be changed similarly
MST2/3 is supported for MDSS1 DPTX0.
>
> [...]
>
>> dispcc1: clock-controller@22100000 {
>> @@ -6872,6 +7115,8 @@ dispcc1: clock-controller@22100000 {
>> <&rpmhcc RPMH_CXO_CLK>,
>> <&rpmhcc RPMH_CXO_CLK_A>,
>> <&sleep_clk>,
>> + <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>,
>> + <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>,
>> <0>, <0>, <0>, <0>,
>
> You need to remove the same amount of zeroes that you added
>
Sure, Will update this in the next version.
> Konrad
>
>> <0>, <0>, <0>, <0>;
>> power-domains = <&rpmhpd SA8775P_MMCX>;
On Thu, Nov 20, 2025 at 02:25:01PM +0530, Mani Chandana Kuntumalla wrote:
>
>
> On 10/8/2025 6:10 PM, Konrad Dybcio wrote:
> > On 9/26/25 10:59 AM, Mani Chandana Ballary Kuntumalla wrote:
> > > Add device tree nodes for the mdss1 DPTX0 and DPTX1 controllers
> > > with their corresponding PHYs.
> > >
> > > Signed-off-by: Mani Chandana Ballary Kuntumalla <quic_mkuntuma@quicinc.com>
> > > ---
> >
> > [...]
> >
> > > + mdss1_dp0: displayport-controller@22154000 {
> > > + compatible = "qcom,sa8775p-dp";
> > > +
> > > + reg = <0x0 0x22154000 0x0 0x104>,
> >
> > sz = 0x200
> >
> > > + <0x0 0x22154200 0x0 0x0c0>,
> >
> > sz = 0x200
> >
> > > + <0x0 0x22155000 0x0 0x770>,
> >
> > sz = 0xc00> + <0x0 0x22156000 0x0 0x09c>,
> > > + <0x0 0x22157000 0x0 0x09c>,
> > > + <0x0 0x22158000 0x0 0x09c>,
> > > + <0x0 0x22159000 0x0 0x09c>,
> >
> > sz = 0x400 for all 0x9c
> >
> > > + <0x0 0x2215a000 0x0 0x23c>,
> > > + <0x0 0x2215b000 0x0 0x23c>;
> >
> > 0x23c -> 0x600
> >
> > [...]
> >
> >
> > > + mdss1_dp1: displayport-controller@2215c000 {
> > > + compatible = "qcom,sa8775p-dp";
> > > +
> > > + reg = <0x0 0x2215c000 0x0 0x104>,
> > > + <0x0 0x2215c200 0x0 0x0c0>,
> > > + <0x0 0x2215d000 0x0 0x770>,
> > > + <0x0 0x2215e000 0x0 0x09c>,
> > > + <0x0 0x2215f000 0x0 0x09c>,
> > > + <0x0 0x22160000 0x0 0x09c>,
> > > + <0x0 0x22161000 0x0 0x09c>,
> > > + <0x0 0x22162000 0x0 0x23c>,
> > > + <0x0 0x22163000 0x0 0x23c>;
> >
> > 0x2216_2000 and _3000 don't exist, there's no MST2/3
> >
> > sizes should be changed similarly
>
> MST2/3 is supported for MDSS1 DPTX0.
This is MDSS1 DPTX1
--
With best wishes
Dmitry
On Wed, Oct 08, 2025 at 02:40:35PM +0200, Konrad Dybcio wrote:
> On 9/26/25 10:59 AM, Mani Chandana Ballary Kuntumalla wrote:
> > Add device tree nodes for the mdss1 DPTX0 and DPTX1 controllers
> > with their corresponding PHYs.
> >
> > Signed-off-by: Mani Chandana Ballary Kuntumalla <quic_mkuntuma@quicinc.com>
> > ---
>
> [...]
>
> > + mdss1_dp0: displayport-controller@22154000 {
> > + compatible = "qcom,sa8775p-dp";
> > +
> > + reg = <0x0 0x22154000 0x0 0x104>,
>
> sz = 0x200
Hmm, why? I think the memory map specifies these sizes.
>
>
> > + mdss1_dp1: displayport-controller@2215c000 {
> > + compatible = "qcom,sa8775p-dp";
> > +
> > + reg = <0x0 0x2215c000 0x0 0x104>,
> > + <0x0 0x2215c200 0x0 0x0c0>,
> > + <0x0 0x2215d000 0x0 0x770>,
> > + <0x0 0x2215e000 0x0 0x09c>,
> > + <0x0 0x2215f000 0x0 0x09c>,
> > + <0x0 0x22160000 0x0 0x09c>,
> > + <0x0 0x22161000 0x0 0x09c>,
> > + <0x0 0x22162000 0x0 0x23c>,
> > + <0x0 0x22163000 0x0 0x23c>;
>
> 0x2216_2000 and _3000 don't exist, there's no MST2/3
Hmm, I will need to check this...
>
> sizes should be changed similarly
>
> [...]
>
> > dispcc1: clock-controller@22100000 {
> > @@ -6872,6 +7115,8 @@ dispcc1: clock-controller@22100000 {
> > <&rpmhcc RPMH_CXO_CLK>,
> > <&rpmhcc RPMH_CXO_CLK_A>,
> > <&sleep_clk>,
> > + <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>,
> > + <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>,
> > <0>, <0>, <0>, <0>,
>
> You need to remove the same amount of zeroes that you added
Nice catch. Which means that somebody was sending untested patches.
Nice.
--
With best wishes
Dmitry
On 10/8/25 2:49 PM, Dmitry Baryshkov wrote:
> On Wed, Oct 08, 2025 at 02:40:35PM +0200, Konrad Dybcio wrote:
>> On 9/26/25 10:59 AM, Mani Chandana Ballary Kuntumalla wrote:
>>> Add device tree nodes for the mdss1 DPTX0 and DPTX1 controllers
>>> with their corresponding PHYs.
>>>
>>> Signed-off-by: Mani Chandana Ballary Kuntumalla <quic_mkuntuma@quicinc.com>
>>> ---
>>
>> [...]
>>
>>> + mdss1_dp0: displayport-controller@22154000 {
>>> + compatible = "qcom,sa8775p-dp";
>>> +
>>> + reg = <0x0 0x22154000 0x0 0x104>,
>>
>> sz = 0x200
>
> Hmm, why? I think the memory map specifies these sizes.
Yeah and I went in line with the allocated region size (not last register)
[...]
>>> dispcc1: clock-controller@22100000 {
>>> @@ -6872,6 +7115,8 @@ dispcc1: clock-controller@22100000 {
>>> <&rpmhcc RPMH_CXO_CLK>,
>>> <&rpmhcc RPMH_CXO_CLK_A>,
>>> <&sleep_clk>,
>>> + <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>,
>>> + <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>,
>>> <0>, <0>, <0>, <0>,
>>
>> You need to remove the same amount of zeroes that you added
>
> Nice catch. Which means that somebody was sending untested patches.
It would work.. until someone tried to add DSI to the second row of zeroes
instead of the first one
Konrad> Nice.
>
On Wed, Oct 08, 2025 at 02:50:45PM +0200, Konrad Dybcio wrote:
> On 10/8/25 2:49 PM, Dmitry Baryshkov wrote:
> > On Wed, Oct 08, 2025 at 02:40:35PM +0200, Konrad Dybcio wrote:
> >> On 9/26/25 10:59 AM, Mani Chandana Ballary Kuntumalla wrote:
> >>> Add device tree nodes for the mdss1 DPTX0 and DPTX1 controllers
> >>> with their corresponding PHYs.
> >>>
> >>> Signed-off-by: Mani Chandana Ballary Kuntumalla <quic_mkuntuma@quicinc.com>
> >>> ---
> >>
> >> [...]
> >>
> >>> + mdss1_dp0: displayport-controller@22154000 {
> >>> + compatible = "qcom,sa8775p-dp";
> >>> +
> >>> + reg = <0x0 0x22154000 0x0 0x104>,
> >>
> >> sz = 0x200
> >
> > Hmm, why? I think the memory map specifies these sizes.
>
> Yeah and I went in line with the allocated region size (not last register)
And this goes against the practice used for DP controllers on other
platforms (or other DP controllers on this platform FWIW).
>
> [...]
>
> >>> dispcc1: clock-controller@22100000 {
> >>> @@ -6872,6 +7115,8 @@ dispcc1: clock-controller@22100000 {
> >>> <&rpmhcc RPMH_CXO_CLK>,
> >>> <&rpmhcc RPMH_CXO_CLK_A>,
> >>> <&sleep_clk>,
> >>> + <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>,
> >>> + <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>,
> >>> <0>, <0>, <0>, <0>,
> >>
> >> You need to remove the same amount of zeroes that you added
> >
> > Nice catch. Which means that somebody was sending untested patches.
>
> It would work.. until someone tried to add DSI to the second row of zeroes
> instead of the first one
I meant tested against bindings.
--
With best wishes
Dmitry
On Fri, Sep 26, 2025 at 02:29:54PM +0530, Mani Chandana Ballary Kuntumalla wrote: > Add device tree nodes for the mdss1 DPTX0 and DPTX1 controllers > with their corresponding PHYs. > > Signed-off-by: Mani Chandana Ballary Kuntumalla <quic_mkuntuma@quicinc.com> > --- > arch/arm64/boot/dts/qcom/lemans.dtsi | 245 +++++++++++++++++++++++++++ > 1 file changed, 245 insertions(+) > Squash together with the series adding mdss1. There should be exactly three patches: fix for DP, addition of mdss1 to the lemans.dtsi, addition of mdss1 to lemans-ride.dtsi. -- With best wishes Dmitry
On 9/26/2025 7:23 PM, Dmitry Baryshkov wrote: > On Fri, Sep 26, 2025 at 02:29:54PM +0530, Mani Chandana Ballary Kuntumalla wrote: >> Add device tree nodes for the mdss1 DPTX0 and DPTX1 controllers >> with their corresponding PHYs. >> >> Signed-off-by: Mani Chandana Ballary Kuntumalla <quic_mkuntuma@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/lemans.dtsi | 245 +++++++++++++++++++++++++++ >> 1 file changed, 245 insertions(+) >> > > Squash together with the series adding mdss1. There should be exactly > three patches: fix for DP, addition of mdss1 to the lemans.dtsi, > addition of mdss1 to lemans-ride.dtsi. > Sure, we will update the patches as per your suggestion.
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