Add pcie_4l_phy, pcie_2l_phy dt node for all PCIe PHY instances
in ExynosAutov920 SoC.

Add HSI sysreg to control PCIe sysreg registers.

Signed-off-by: Sanghoon Bae <sh86.bae@samsung.com>
---
 .../arm64/boot/dts/exynos/exynosautov920.dtsi | 28 +++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
index 2cb8041c8a9f..9e45bfcd7980 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
@@ -1021,12 +1021,40 @@ cmu_hsi0: clock-controller@16000000 {
 				      "noc";
 		};
 
+		syscon_hsi0: syscon@16030000 {
+			compatible = "samsung,exynosautov920-hsi0-sysreg",
+				     "syscon";
+			reg = <0x16030000 0x1000>;
+		};
+
 		pinctrl_hsi0: pinctrl@16040000 {
 			compatible = "samsung,exynosautov920-pinctrl";
 			reg = <0x16040000 0x10000>;
 			interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		pcie_2l_phy: pcie-phy2l@161c6000{
+			compatible = "samsung,exynosautov920-pcie-phy";
+			reg = <0x161c6000 0x2000>,
+			      <0x161d0000 0xb000>;
+			#phy-cells = <0>;
+			samsung,pmu-syscon = <&pmu_system_controller>;
+			samsung,fsys-sysreg = <&syscon_hsi0>;
+			num-lanes = <2>;
+			status = "disabled";
+		};
+
+		pcie_4l_phy: pcie-phy4l@163c6000{
+			compatible = "samsung,exynosautov920-pcie-phy";
+			reg = <0x163c6000 0x2000>,
+			      <0x163d0000 0xb000>;
+			#phy-cells = <0>;
+			samsung,pmu-syscon = <&pmu_system_controller>;
+			samsung,fsys-sysreg = <&syscon_hsi0>;
+			num-lanes = <4>;
+			status = "disabled";
+		};
+
 		cmu_hsi1: clock-controller@16400000 {
 			compatible = "samsung,exynosautov920-cmu-hsi1";
 			reg = <0x16400000 0x8000>;
-- 
2.45.2

On 26/09/2025 16:39, Sanghoon Bae wrote:
> Add pcie_4l_phy, pcie_2l_phy dt node for all PCIe PHY instances
> in ExynosAutov920 SoC.
> 
> Add HSI sysreg to control PCIe sysreg registers.
> 
> Signed-off-by: Sanghoon Bae <sh86.bae@samsung.com>
> ---
>  .../arm64/boot/dts/exynos/exynosautov920.dtsi | 28 +++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> index 2cb8041c8a9f..9e45bfcd7980 100644
> --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> @@ -1021,12 +1021,40 @@ cmu_hsi0: clock-controller@16000000 {
>  				      "noc";
>  		};
>  
> +		syscon_hsi0: syscon@16030000 {
> +			compatible = "samsung,exynosautov920-hsi0-sysreg",
> +				     "syscon";
> +			reg = <0x16030000 0x1000>;
> +		};
> +
>  		pinctrl_hsi0: pinctrl@16040000 {
>  			compatible = "samsung,exynosautov920-pinctrl";
>  			reg = <0x16040000 0x10000>;
>  			interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
>  		};
>  
> +		pcie_2l_phy: pcie-phy2l@161c6000{



Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
If you cannot find a name matching your device, please check in kernel
sources for similar cases or you can grow the spec (via pull request to
DT spec repo).

Plus style issues... missing space.

I would like to see also PCIe nodes somewhere, because I wonder if
num-lanes should not be moved to PCI node (phy consumer) instead.
Current approach feels better, but maybe it just duplicates num-lanes
from the PCI?

Best regards,
Krzysztof

> > +		pcie_2l_phy: pcie-phy2l@161c6000{
> 
> 
> 
> Node names should be generic. See also an explanation and list of examples
> (not exhaustive) in DT specification:
> https://protect2.fireeye.com/v1/url?k=d2bcf1f2-8d273f96-d2bd7abd-
> 000babda0201-1fe7eb4ecd262f65&q=1&e=8522e96d-f1a1-4b6b-baa9-
> 44344340469a&u=https%3A%2F%2Fdevicetree-
> specification.readthedocs.io%2Fen%2Flatest%2Fchapter2-devicetree-
> basics.html%23generic-names-recommendation
> If you cannot find a name matching your device, please check in kernel
> sources for similar cases or you can grow the spec (via pull request to DT
> spec repo).
I will rename the node referring the guideline you linked.

> Plus style issues... missing space.
Will add space before left brace.

> I would like to see also PCIe nodes somewhere, because I wonder if num-
> lanes should not be moved to PCI node (phy consumer) instead.
> Current approach feels better, but maybe it just duplicates num-lanes from
> the PCI?
As mentioned earlier, I plan to enable the PCIe nodes later.
However, I can share my prototype PCIe node that I am currently using for
PCIe driver testing:

pcie_0: pcie@163c0000 {
	compatible = "samsung,exynosautov920-pcie";
	gpios = <&gph0 1 0>;	/* PERST */
	reg = <0x163C0000 0x1000>, <0x12000000 0x20000>,
		<0x2fffd000 0x2000>, <0x12600000 0x2000>;
	reg-names = "elbi", "dbi", "config", "atu";
	#address-cells = <3>;
	#size-cells = <2>;
	#interrupt-cells = <1>;
	device_type = "pci";
	interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&xtcxo>;
	clock-names = "ref_clk";
	num-lanes = <1>;
	num-viewport = <3>;
	bus-range = <0x00 0xff>;
	phys = <&pcie_0_phy>;
	samsung,pcie-ch = <0>;
	ranges = <0x82000000 0 0x20000000 0x20000000 0 0x1FFFD000>;
	status = "disabled";
};

As you expected, num-lanes will be defined only in the PCIe node.
Please let me know if this composition of the DT nodes looks appropriate
to you.