The MDSS (Mobile Display SubSystem) on Glymur comes with 4 DisplayPort
controllers. Describe them along with display controller and the eDP
PHY. Then, attach the combo PHYs link and vco_div clocks to the Display
clock controller and link up the PHYs and DP endpoints in the graph.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 492 ++++++++++++++++++++++++++++++++++-
1 file changed, 484 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index a131cd6c3d9e7f14ed1c4aef4b68e1860cc3bca5..41d89998b1fe14a24cd528e73afc37cf2a840bab 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -2698,6 +2698,7 @@ port@2 {
reg = <2>;
usb_dp_qmpphy_dp_in: endpoint {
+ remote-endpoint = <&mdss_dp0_out>;
};
};
};
@@ -2766,11 +2767,34 @@ port@2 {
reg = <2>;
usb_1_ss1_qmpphy_dp_in: endpoint {
+ remote-endpoint = <&mdss_dp1_out>;
};
};
};
};
+ mdss_dp3_phy: phy@faac00 {
+ compatible = "qcom,glymur-dp-phy";
+ reg = <0 0x00faac00 0 0x1d0>,
+ <0 0x00faa400 0 0x128>,
+ <0 0x00faa800 0 0x128>,
+ <0 0x00faa000 0 0x358>;
+
+ clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&tcsrcc TCSR_EDP_CLKREF_EN>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref";
+
+ power-domains = <&rpmhpd RPMHPD_MX>;
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
cnoc_main: interconnect@1500000 {
compatible = "qcom,glymur-cnoc-main";
reg = <0x0 0x01500000 0x0 0x17080>;
@@ -3248,6 +3272,7 @@ port@2 {
reg = <2>;
usb_1_ss2_qmpphy_dp_in: endpoint {
+ remote-endpoint = <&mdss_dp2_out>;
};
};
};
@@ -3523,7 +3548,458 @@ usb_mp: usb@a400000 {
dr_mode = "host";
status = "disabled";
+ };
+
+ mdss: display-subsystem@ae00000 {
+ compatible = "qcom,glymur-mdss";
+ reg = <0x0 0x0ae00000 0x0 0x1000>;
+ reg-names = "mdss";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+
+ resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
+ interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "mdp0-mem",
+ "cpu-cfg";
+
+ power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
+
+ iommus = <&apps_smmu 0x1de0 0x2>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ mdss_mdp: display-controller@ae01000 {
+ compatible = "qcom,glymur-dpu";
+ reg = <0 0x0ae01000 0 0x93000>,
+ <0 0x0aeb0000 0 0x2008>;
+ reg-names = "mdp",
+ "vbif";
+
+ interrupts-extended = <&mdss 0>;
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ operating-points-v2 = <&mdp_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dpu_intf0_out: endpoint {
+ remote-endpoint = <&mdss_dp0_in>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ mdss_intf4_out: endpoint {
+ remote-endpoint = <&mdss_dp1_in>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+
+ mdss_intf5_out: endpoint {
+ remote-endpoint = <&mdss_dp3_in>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+
+ mdss_intf6_out: endpoint {
+ remote-endpoint = <&mdss_dp2_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-205000000 {
+ opp-hz = /bits/ 64 <205000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-337000000 {
+ opp-hz = /bits/ 64 <337000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-417000000 {
+ opp-hz = /bits/ 64 <417000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-532000000 {
+ opp-hz = /bits/ 64 <532000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ required-opps = <&rpmhpd_opp_nom_l1>;
+ };
+ };
+ };
+
+ mdss_dp0: displayport-controller@af54000 {
+ compatible = "qcom,glymur-dp";
+ reg = <0x0 0xaf54000 0x0 0x104>,
+ <0x0 0xaf54200 0x0 0xc0>,
+ <0x0 0xaf55000 0x0 0x770>,
+ <0x0 0xaf56000 0x0 0x9c>,
+ <0x0 0xaf57000 0x0 0x9c>;
+
+ interrupts-extended = <&mdss 12>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+ assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
+
+ operating-points-v2 = <&mdss_dp0_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>;
+ phy-names = "dp";
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dp0_in: endpoint {
+ remote-endpoint = <&dpu_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dp0_out: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_dp_in>;
+ };
+ };
+ };
+
+ mdss_dp0_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-192000000 {
+ opp-hz = /bits/ 64 <192000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ mdss_dp1: displayport-controller@af5c000 {
+ compatible = "qcom,glymur-dp", "qcom,sm8650-dp";
+ reg = <0x0 0xaf5c000 0x0 0x104>,
+ <0x0 0xaf5c200 0x0 0xc0>,
+ <0x0 0xaf5d000 0x0 0x770>,
+ <0x0 0xaf5e000 0x0 0x9c>,
+ <0x0 0xaf5f000 0x0 0x9c>;
+
+ interrupts-extended = <&mdss 13>;
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
+ assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
+
+ operating-points-v2 = <&mdss_dp1_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>;
+ phy-names = "dp";
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dp1_in: endpoint {
+ remote-endpoint = <&mdss_intf4_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dp1_out: endpoint {
+ remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>;
+ };
+ };
+ };
+
+ mdss_dp1_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-192000000 {
+ opp-hz = /bits/ 64 <192000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d1>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ mdss_dp2: displayport-controller@af64000 {
+ compatible = "qcom,glymur-dp";
+ reg = <0x0 0x0af64000 0x0 0x104>,
+ <0x0 0x0af64200 0x0 0xc0>,
+ <0x0 0x0af65000 0x0 0x770>,
+ <0x0 0x0af66000 0x0 0x9c>,
+ <0x0 0x0af67000 0x0 0x9c>;
+
+ interrupts-extended = <&mdss 14>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
+ assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
+
+ operating-points-v2 = <&mdss_dp2_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ phys = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_PHY>;
+ phy-names = "dp";
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dp2_in: endpoint {
+ remote-endpoint = <&mdss_intf6_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dp2_out: endpoint {
+ remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>;
+ };
+ };
+ };
+
+ mdss_dp2_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ mdss_dp3: displayport-controller@af6c000 {
+ compatible = "qcom,glymur-dp";
+ reg = <0 0x0af6c000 0 0x200>,
+ <0 0x0af6c200 0 0x200>,
+ <0 0x0af6d000 0 0xc00>,
+ <0 0x0af6e000 0 0x400>,
+ <0 0x0af6f000 0 0x400>;
+
+ interrupts-extended = <&mdss 15>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dp3_phy 0>,
+ <&mdss_dp3_phy 1>;
+
+ operating-points-v2 = <&mdss_dp3_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ phys = <&mdss_dp3_phy>;
+ phy-names = "dp";
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dp3_in: endpoint {
+ remote-endpoint = <&mdss_intf5_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+
+ mdss_dp3_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
};
dispcc: clock-controller@af00000 {
@@ -3531,14 +4007,14 @@ dispcc: clock-controller@af00000 {
reg = <0 0x0af00000 0 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>,
- <0>, /* dp0 */
- <0>,
- <0>, /* dp1 */
- <0>,
- <0>, /* dp2 */
- <0>,
- <0>, /* dp3 */
- <0>,
+ <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */
+ <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
+ <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */
+ <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
+ <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */
+ <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
+ <&mdss_dp3_phy 0>, /* dp3 */
+ <&mdss_dp3_phy 1>,
<0>, /* dsi0 */
<0>,
<0>, /* dsi1 */
--
2.48.1On Thu, Sep 25, 2025 at 06:02:48PM +0300, Abel Vesa wrote:
> The MDSS (Mobile Display SubSystem) on Glymur comes with 4 DisplayPort
> controllers. Describe them along with display controller and the eDP
> PHY. Then, attach the combo PHYs link and vco_div clocks to the Display
> clock controller and link up the PHYs and DP endpoints in the graph.
>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/glymur.dtsi | 492 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 484 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index a131cd6c3d9e7f14ed1c4aef4b68e1860cc3bca5..41d89998b1fe14a24cd528e73afc37cf2a840bab 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -2698,6 +2698,7 @@ port@2 {
> reg = <2>;
>
> usb_dp_qmpphy_dp_in: endpoint {
> + remote-endpoint = <&mdss_dp0_out>;
> };
> };
> };
> @@ -2766,11 +2767,34 @@ port@2 {
> reg = <2>;
>
> usb_1_ss1_qmpphy_dp_in: endpoint {
> + remote-endpoint = <&mdss_dp1_out>;
> };
> };
> };
> };
>
> + mdss_dp3_phy: phy@faac00 {
> + compatible = "qcom,glymur-dp-phy";
> + reg = <0 0x00faac00 0 0x1d0>,
> + <0 0x00faa400 0 0x128>,
> + <0 0x00faa800 0 0x128>,
> + <0 0x00faa000 0 0x358>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&tcsrcc TCSR_EDP_CLKREF_EN>;
> + clock-names = "aux",
> + "cfg_ahb",
> + "ref";
> +
> + power-domains = <&rpmhpd RPMHPD_MX>;
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> cnoc_main: interconnect@1500000 {
> compatible = "qcom,glymur-cnoc-main";
> reg = <0x0 0x01500000 0x0 0x17080>;
> @@ -3248,6 +3272,7 @@ port@2 {
> reg = <2>;
>
> usb_1_ss2_qmpphy_dp_in: endpoint {
> + remote-endpoint = <&mdss_dp2_out>;
> };
> };
> };
> @@ -3523,7 +3548,458 @@ usb_mp: usb@a400000 {
> dr_mode = "host";
>
> status = "disabled";
> + };
> +
> + mdss: display-subsystem@ae00000 {
> + compatible = "qcom,glymur-mdss";
> + reg = <0x0 0x0ae00000 0x0 0x1000>;
> + reg-names = "mdss";
> +
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>;
> +
> + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
> +
> + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
> + interconnect-names = "mdp0-mem",
> + "cpu-cfg";
> +
> + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
> +
> + iommus = <&apps_smmu 0x1de0 0x2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + status = "disabled";
> +
> + mdss_mdp: display-controller@ae01000 {
> + compatible = "qcom,glymur-dpu";
> + reg = <0 0x0ae01000 0 0x93000>,
> + <0 0x0aeb0000 0 0x2008>;
> + reg-names = "mdp",
> + "vbif";
> +
> + interrupts-extended = <&mdss 0>;
> +
> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "nrt_bus",
> + "iface",
> + "lut",
> + "core",
> + "vsync";
> +
> + operating-points-v2 = <&mdp_opp_table>;
> +
> + power-domains = <&rpmhpd RPMHPD_MMCX>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + dpu_intf0_out: endpoint {
> + remote-endpoint = <&mdss_dp0_in>;
> + };
> + };
> +
> + port@4 {
> + reg = <4>;
> +
> + mdss_intf4_out: endpoint {
> + remote-endpoint = <&mdss_dp1_in>;
> + };
> + };
> +
> + port@5 {
> + reg = <5>;
> +
> + mdss_intf5_out: endpoint {
> + remote-endpoint = <&mdss_dp3_in>;
> + };
> + };
> +
> + port@6 {
> + reg = <6>;
> +
> + mdss_intf6_out: endpoint {
> + remote-endpoint = <&mdss_dp2_in>;
> + };
> + };
> + };
> +
> + mdp_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-205000000 {
> + opp-hz = /bits/ 64 <205000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-337000000 {
> + opp-hz = /bits/ 64 <337000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-417000000 {
> + opp-hz = /bits/ 64 <417000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-532000000 {
> + opp-hz = /bits/ 64 <532000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> +
> + opp-600000000 {
> + opp-hz = /bits/ 64 <600000000>;
> + required-opps = <&rpmhpd_opp_nom_l1>;
> + };
> + };
> + };
> +
> + mdss_dp0: displayport-controller@af54000 {
> + compatible = "qcom,glymur-dp";
> + reg = <0x0 0xaf54000 0x0 0x104>,
> + <0x0 0xaf54200 0x0 0xc0>,
> + <0x0 0xaf55000 0x0 0x770>,
> + <0x0 0xaf56000 0x0 0x9c>,
> + <0x0 0xaf57000 0x0 0x9c>;
> +
> + interrupts-extended = <&mdss 12>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
No pixel1 clock?
> + clock-names = "core_iface",
> + "core_aux",
> + "ctrl_link",
> + "ctrl_link_iface",
> + "stream_pixel";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
> + assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
No pixel1 clock?
> +
> + operating-points-v2 = <&mdss_dp0_opp_table>;
> +
> + power-domains = <&rpmhpd RPMHPD_MMCX>;
> +
> + phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>;
> + phy-names = "dp";
> +
> + #sound-dai-cells = <0>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + mdss_dp0_in: endpoint {
> + remote-endpoint = <&dpu_intf0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + mdss_dp0_out: endpoint {
> + remote-endpoint = <&usb_dp_qmpphy_dp_in>;
> + };
> + };
> + };
> +
> + mdss_dp0_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-192000000 {
> + opp-hz = /bits/ 64 <192000000>;
> + required-opps = <&rpmhpd_opp_low_svs_d1>;
> + };
> +
> + opp-270000000 {
> + opp-hz = /bits/ 64 <270000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-540000000 {
> + opp-hz = /bits/ 64 <540000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-810000000 {
> + opp-hz = /bits/ 64 <810000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> + };
> +
> + mdss_dp1: displayport-controller@af5c000 {
> + compatible = "qcom,glymur-dp", "qcom,sm8650-dp";
This doesn't match your own bindings. WT?
> + reg = <0x0 0xaf5c000 0x0 0x104>,
> + <0x0 0xaf5c200 0x0 0xc0>,
> + <0x0 0xaf5d000 0x0 0x770>,
> + <0x0 0xaf5e000 0x0 0x9c>,
> + <0x0 0xaf5f000 0x0 0x9c>;
> +
> + interrupts-extended = <&mdss 13>;
>
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
pixel1
> + clock-names = "core_iface",
> + "core_aux",
> + "ctrl_link",
> + "ctrl_link_iface",
> + "stream_pixel";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
> + assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
pixel1
> +
> + operating-points-v2 = <&mdss_dp1_opp_table>;
> +
> + power-domains = <&rpmhpd RPMHPD_MMCX>;
> +
> + phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>;
> + phy-names = "dp";
> +
> + #sound-dai-cells = <0>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + mdss_dp1_in: endpoint {
> + remote-endpoint = <&mdss_intf4_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + mdss_dp1_out: endpoint {
> + remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>;
> + };
> + };
> + };
> +
> + mdss_dp1_opp_table: opp-table {
> + compatible = "operating-points-v2";
Is it differnt from dp0 table?
> +
> + opp-192000000 {
> + opp-hz = /bits/ 64 <192000000>;
> + required-opps = <&rpmhpd_opp_low_svs_d1>;
> + };
> +
> + opp-270000000 {
> + opp-hz = /bits/ 64 <270000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-540000000 {
> + opp-hz = /bits/ 64 <540000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-810000000 {
> + opp-hz = /bits/ 64 <810000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> + };
> +
> + mdss_dp2: displayport-controller@af64000 {
> + compatible = "qcom,glymur-dp";
> + reg = <0x0 0x0af64000 0x0 0x104>,
> + <0x0 0x0af64200 0x0 0xc0>,
> + <0x0 0x0af65000 0x0 0x770>,
> + <0x0 0x0af66000 0x0 0x9c>,
> + <0x0 0x0af67000 0x0 0x9c>;
> +
> + interrupts-extended = <&mdss 14>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
pixel1 clock
> + clock-names = "core_iface",
> + "core_aux",
> + "ctrl_link",
> + "ctrl_link_iface",
> + "stream_pixel";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
> + assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
pixel1
> +
> + operating-points-v2 = <&mdss_dp2_opp_table>;
> +
> + power-domains = <&rpmhpd RPMHPD_MMCX>;
> +
> + phys = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_PHY>;
> + phy-names = "dp";
> +
> + #sound-dai-cells = <0>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + mdss_dp2_in: endpoint {
> + remote-endpoint = <&mdss_intf6_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + mdss_dp2_out: endpoint {
> + remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>;
> + };
> + };
> + };
> +
> + mdss_dp2_opp_table: opp-table {
Different from dp0?
> + compatible = "operating-points-v2";
> +
> + opp-160000000 {
> + opp-hz = /bits/ 64 <160000000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-270000000 {
> + opp-hz = /bits/ 64 <270000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-540000000 {
> + opp-hz = /bits/ 64 <540000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-810000000 {
> + opp-hz = /bits/ 64 <810000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> + };
> +
--
With best wishes
Dmitry
On 25-09-25 20:11:11, Dmitry Baryshkov wrote:
> On Thu, Sep 25, 2025 at 06:02:48PM +0300, Abel Vesa wrote:
> > The MDSS (Mobile Display SubSystem) on Glymur comes with 4 DisplayPort
> > controllers. Describe them along with display controller and the eDP
> > PHY. Then, attach the combo PHYs link and vco_div clocks to the Display
> > clock controller and link up the PHYs and DP endpoints in the graph.
> >
> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> > ---
> > arch/arm64/boot/dts/qcom/glymur.dtsi | 492 ++++++++++++++++++++++++++++++++++-
> > 1 file changed, 484 insertions(+), 8 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > index a131cd6c3d9e7f14ed1c4aef4b68e1860cc3bca5..41d89998b1fe14a24cd528e73afc37cf2a840bab 100644
> > --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
[...]
> > + mdss_dp0: displayport-controller@af54000 {
> > + compatible = "qcom,glymur-dp";
> > + reg = <0x0 0xaf54000 0x0 0x104>,
> > + <0x0 0xaf54200 0x0 0xc0>,
> > + <0x0 0xaf55000 0x0 0x770>,
> > + <0x0 0xaf56000 0x0 0x9c>,
> > + <0x0 0xaf57000 0x0 0x9c>;
> > +
> > + interrupts-extended = <&mdss 12>;
> > +
> > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
> > + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
> > + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
> > + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
>
> No pixel1 clock?
Will add it in next version. Everywhere.
> > +
> > + mdss_dp1: displayport-controller@af5c000 {
> > + compatible = "qcom,glymur-dp", "qcom,sm8650-dp";
>
> This doesn't match your own bindings. WT?
Urgh. Yep, this is wrong. sm8650 compatible needs to be dropped. Will do
in the next version.
> > +
> > + mdss_dp1_opp_table: opp-table {
> > + compatible = "operating-points-v2";
>
> Is it differnt from dp0 table?
Nope, they are the same. Will use the dp0 table for all controllers.
Thanks for reviewing.
Abel
On Fri, Sep 26, 2025 at 09:50:22AM +0300, Abel Vesa wrote:
> On 25-09-25 20:11:11, Dmitry Baryshkov wrote:
> > On Thu, Sep 25, 2025 at 06:02:48PM +0300, Abel Vesa wrote:
> > > The MDSS (Mobile Display SubSystem) on Glymur comes with 4 DisplayPort
> > > controllers. Describe them along with display controller and the eDP
> > > PHY. Then, attach the combo PHYs link and vco_div clocks to the Display
> > > clock controller and link up the PHYs and DP endpoints in the graph.
> > >
> > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> > > ---
> > > arch/arm64/boot/dts/qcom/glymur.dtsi | 492 ++++++++++++++++++++++++++++++++++-
> > > 1 file changed, 484 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > > index a131cd6c3d9e7f14ed1c4aef4b68e1860cc3bca5..41d89998b1fe14a24cd528e73afc37cf2a840bab 100644
> > > --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
>
> [...]
>
> > > + mdss_dp0: displayport-controller@af54000 {
> > > + compatible = "qcom,glymur-dp";
> > > + reg = <0x0 0xaf54000 0x0 0x104>,
> > > + <0x0 0xaf54200 0x0 0xc0>,
> > > + <0x0 0xaf55000 0x0 0x770>,
> > > + <0x0 0xaf56000 0x0 0x9c>,
> > > + <0x0 0xaf57000 0x0 0x9c>;
> > > +
> > > + interrupts-extended = <&mdss 12>;
> > > +
> > > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > > + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
> > > + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
> > > + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
> > > + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
> >
> > No pixel1 clock?
>
> Will add it in next version. Everywhere.
Except DP3, if I'm not mistaken.
>
> > > +
> > > + mdss_dp1: displayport-controller@af5c000 {
> > > + compatible = "qcom,glymur-dp", "qcom,sm8650-dp";
> >
> > This doesn't match your own bindings. WT?
>
> Urgh. Yep, this is wrong. sm8650 compatible needs to be dropped. Will do
> in the next version.
>
> > > +
> > > + mdss_dp1_opp_table: opp-table {
> > > + compatible = "operating-points-v2";
> >
> > Is it differnt from dp0 table?
>
> Nope, they are the same. Will use the dp0 table for all controllers.
>
> Thanks for reviewing.
>
> Abel
--
With best wishes
Dmitry
On 9/27/25 12:33 AM, Dmitry Baryshkov wrote:
> On Fri, Sep 26, 2025 at 09:50:22AM +0300, Abel Vesa wrote:
>> On 25-09-25 20:11:11, Dmitry Baryshkov wrote:
>>> On Thu, Sep 25, 2025 at 06:02:48PM +0300, Abel Vesa wrote:
>>>> The MDSS (Mobile Display SubSystem) on Glymur comes with 4 DisplayPort
>>>> controllers. Describe them along with display controller and the eDP
>>>> PHY. Then, attach the combo PHYs link and vco_div clocks to the Display
>>>> clock controller and link up the PHYs and DP endpoints in the graph.
>>>>
>>>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/glymur.dtsi | 492 ++++++++++++++++++++++++++++++++++-
>>>> 1 file changed, 484 insertions(+), 8 deletions(-)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
>>>> index a131cd6c3d9e7f14ed1c4aef4b68e1860cc3bca5..41d89998b1fe14a24cd528e73afc37cf2a840bab 100644
>>>> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
>>
>> [...]
>>
>>>> + mdss_dp0: displayport-controller@af54000 {
>>>> + compatible = "qcom,glymur-dp";
>>>> + reg = <0x0 0xaf54000 0x0 0x104>,
>>>> + <0x0 0xaf54200 0x0 0xc0>,
>>>> + <0x0 0xaf55000 0x0 0x770>,
>>>> + <0x0 0xaf56000 0x0 0x9c>,
>>>> + <0x0 0xaf57000 0x0 0x9c>;
>>>> +
>>>> + interrupts-extended = <&mdss 12>;
>>>> +
>>>> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
>>>> + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
>>>> + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
>>>> + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
>>>> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
>>>
>>> No pixel1 clock?
>>
>> Will add it in next version. Everywhere.
>
> Except DP3, if I'm not mistaken.
$ rg PIXEL1 drivers/clk/qcom/dispcc-glymur.c
1841: [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr,
1842: [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr,
1855: [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr,
1856: [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr,
1869: [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr,
1870: [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr,
looks like it
Konrad
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