clk: qcom: gcc-sm8750: Add a new frequency for sdcc2 clock

[PATCH] clk: qcom: gcc-sm8750: Add a new frequency for sdcc2 clock

Posted by Taniya Das 4 months, 2 weeks ago

The SD card support requires a 37.5MHz clock; add it to the frequency
list for the storage SW driver to be able to request for the frequency.

Fixes: 3267c774f3ff ("clk: qcom: Add support for GCC on SM8750")
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sm8750.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sm8750.c b/drivers/clk/qcom/gcc-sm8750.c
index 8092dd6b37b56f4fd786e33d4f0e8aabcd6ecdfe..def86b71a3da534f07844f01ecb73b424db3bddc 100644
--- a/drivers/clk/qcom/gcc-sm8750.c
+++ b/drivers/clk/qcom/gcc-sm8750.c
@@ -1012,6 +1012,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
 	F(400000, P_BI_TCXO, 12, 1, 4),
 	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
+	F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),
 	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
 	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
 	F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),

---
base-commit: ce7f1a983b074f6cf8609068088ca3182c569ee4
change-id: 20250923-sm8750_gcc_sdcc2_frequency-debfdbbab8b3

Best regards,
-- 
Taniya Das <taniya.das@oss.qualcomm.com>

Re: [PATCH] clk: qcom: gcc-sm8750: Add a new frequency for sdcc2 clock

Posted by Bjorn Andersson 3 months, 2 weeks ago

On Wed, 24 Sep 2025 00:08:30 +0530, Taniya Das wrote:
> The SD card support requires a 37.5MHz clock; add it to the frequency
> list for the storage SW driver to be able to request for the frequency.
> 
> 

Applied, thanks!

[1/1] clk: qcom: gcc-sm8750: Add a new frequency for sdcc2 clock
      commit: 393f7834cd2b1eaf4a9eff2701e706e73e660dd7

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>

Re: [PATCH] clk: qcom: gcc-sm8750: Add a new frequency for sdcc2 clock

Posted by Imran Shaik 4 months, 2 weeks ago


On 9/24/2025 12:08 AM, Taniya Das wrote:
> The SD card support requires a 37.5MHz clock; add it to the frequency
> list for the storage SW driver to be able to request for the frequency.
> 
> Fixes: 3267c774f3ff ("clk: qcom: Add support for GCC on SM8750")
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> ---
>  drivers/clk/qcom/gcc-sm8750.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/clk/qcom/gcc-sm8750.c b/drivers/clk/qcom/gcc-sm8750.c
> index 8092dd6b37b56f4fd786e33d4f0e8aabcd6ecdfe..def86b71a3da534f07844f01ecb73b424db3bddc 100644
> --- a/drivers/clk/qcom/gcc-sm8750.c
> +++ b/drivers/clk/qcom/gcc-sm8750.c
> @@ -1012,6 +1012,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
>  static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
>  	F(400000, P_BI_TCXO, 12, 1, 4),
>  	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
> +	F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),
>  	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
>  	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
>  	F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
> 
> ---
> base-commit: ce7f1a983b074f6cf8609068088ca3182c569ee4
> change-id: 20250923-sm8750_gcc_sdcc2_frequency-debfdbbab8b3
> 
> Best regards,

Reviewed-by: Imran Shaik <imran.shaik@oss.qualcomm.com>

Thanks,
Imran