Add endianness handling to the FIFO access helpers i3c_readl_fifo() and
i3c_writel_fifo(). This ensures correct data transfers on platforms where
the FIFO registers are expected to be accessed in either big-endian or
little-endian format.
Update the Synopsys, Cadence, and Renesas I3C master controller drivers to
pass the appropriate endianness argument to these helpers.
Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com>
---
Changes since V7:
This patch introduced in V7.
---
drivers/i3c/internals.h | 35 +++++++++++++++++++++++-----
drivers/i3c/master/dw-i3c-master.c | 9 ++++---
drivers/i3c/master/i3c-master-cdns.c | 9 ++++---
drivers/i3c/master/renesas-i3c.c | 12 ++++++----
4 files changed, 49 insertions(+), 16 deletions(-)
diff --git a/drivers/i3c/internals.h b/drivers/i3c/internals.h
index 0d857cc68cc5..399bbf006dcd 100644
--- a/drivers/i3c/internals.h
+++ b/drivers/i3c/internals.h
@@ -24,21 +24,35 @@ int i3c_dev_request_ibi_locked(struct i3c_dev_desc *dev,
const struct i3c_ibi_setup *req);
void i3c_dev_free_ibi_locked(struct i3c_dev_desc *dev);
+enum i3c_fifo_endian {
+ I3C_FIFO_LITTLE_ENDIAN,
+ I3C_FIFO_BIG_ENDIAN,
+};
+
/**
* i3c_writel_fifo - Write data buffer to 32bit FIFO
* @addr: FIFO Address to write to
* @buf: Pointer to the data bytes to write
* @nbytes: Number of bytes to write
+ * @endian: Endianness of FIFO write
*/
static inline void i3c_writel_fifo(void __iomem *addr, const void *buf,
- int nbytes)
+ int nbytes, enum i3c_fifo_endian endian)
{
- writesl(addr, buf, nbytes / 4);
+ if (endian)
+ writesl_be(addr, buf, nbytes / 4);
+ else
+ writesl(addr, buf, nbytes / 4);
+
if (nbytes & 3) {
u32 tmp = 0;
memcpy(&tmp, buf + (nbytes & ~3), nbytes & 3);
- writel(tmp, addr);
+
+ if (endian)
+ writel_be(tmp, addr);
+ else
+ writel(tmp, addr);
}
}
@@ -47,15 +61,24 @@ static inline void i3c_writel_fifo(void __iomem *addr, const void *buf,
* @addr: FIFO Address to read from
* @buf: Pointer to the buffer to store read bytes
* @nbytes: Number of bytes to read
+ * @endian: Endianness of FIFO read
*/
static inline void i3c_readl_fifo(const void __iomem *addr, void *buf,
- int nbytes)
+ int nbytes, enum i3c_fifo_endian endian)
{
- readsl(addr, buf, nbytes / 4);
+ if (endian)
+ readsl_be(addr, buf, nbytes / 4);
+ else
+ readsl(addr, buf, nbytes / 4);
+
if (nbytes & 3) {
u32 tmp;
- tmp = readl(addr);
+ if (endian)
+ tmp = readl_be(addr);
+ else
+ tmp = readl(addr);
+
memcpy(buf + (nbytes & ~3), &tmp, nbytes & 3);
}
}
diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c
index 974122b2d20e..5d723ac041c2 100644
--- a/drivers/i3c/master/dw-i3c-master.c
+++ b/drivers/i3c/master/dw-i3c-master.c
@@ -337,19 +337,22 @@ static int dw_i3c_master_get_free_pos(struct dw_i3c_master *master)
static void dw_i3c_master_wr_tx_fifo(struct dw_i3c_master *master,
const u8 *bytes, int nbytes)
{
- i3c_writel_fifo(master->regs + RX_TX_DATA_PORT, bytes, nbytes);
+ i3c_writel_fifo(master->regs + RX_TX_DATA_PORT, bytes, nbytes,
+ I3C_FIFO_LITTLE_ENDIAN);
}
static void dw_i3c_master_read_rx_fifo(struct dw_i3c_master *master,
u8 *bytes, int nbytes)
{
- i3c_readl_fifo(master->regs + RX_TX_DATA_PORT, bytes, nbytes);
+ i3c_readl_fifo(master->regs + RX_TX_DATA_PORT, bytes, nbytes,
+ I3C_FIFO_LITTLE_ENDIAN);
}
static void dw_i3c_master_read_ibi_fifo(struct dw_i3c_master *master,
u8 *bytes, int nbytes)
{
- i3c_readl_fifo(master->regs + IBI_QUEUE_STATUS, bytes, nbytes);
+ i3c_readl_fifo(master->regs + IBI_QUEUE_STATUS, bytes, nbytes,
+ I3C_FIFO_LITTLE_ENDIAN);
}
static struct dw_i3c_xfer *
diff --git a/drivers/i3c/master/i3c-master-cdns.c b/drivers/i3c/master/i3c-master-cdns.c
index 97b151564d3d..de3b5e894b4b 100644
--- a/drivers/i3c/master/i3c-master-cdns.c
+++ b/drivers/i3c/master/i3c-master-cdns.c
@@ -428,13 +428,15 @@ to_cdns_i3c_master(struct i3c_master_controller *master)
static void cdns_i3c_master_wr_to_tx_fifo(struct cdns_i3c_master *master,
const u8 *bytes, int nbytes)
{
- i3c_writel_fifo(master->regs + TX_FIFO, bytes, nbytes);
+ i3c_writel_fifo(master->regs + TX_FIFO, bytes, nbytes,
+ I3C_FIFO_LITTLE_ENDIAN);
}
static void cdns_i3c_master_rd_from_rx_fifo(struct cdns_i3c_master *master,
u8 *bytes, int nbytes)
{
- i3c_readl_fifo(master->regs + RX_FIFO, bytes, nbytes);
+ i3c_readl_fifo(master->regs + RX_FIFO, bytes, nbytes,
+ I3C_FIFO_LITTLE_ENDIAN);
}
static bool cdns_i3c_master_supports_ccc_cmd(struct i3c_master_controller *m,
@@ -1319,7 +1321,8 @@ static void cdns_i3c_master_handle_ibi(struct cdns_i3c_master *master,
buf = slot->data;
nbytes = IBIR_XFER_BYTES(ibir);
- i3c_readl_fifo(master->regs + IBI_DATA_FIFO, buf, nbytes);
+ i3c_readl_fifo(master->regs + IBI_DATA_FIFO, buf, nbytes,
+ I3C_FIFO_LITTLE_ENDIAN);
slot->len = min_t(unsigned int, IBIR_XFER_BYTES(ibir),
dev->ibi->max_payload_len);
diff --git a/drivers/i3c/master/renesas-i3c.c b/drivers/i3c/master/renesas-i3c.c
index 174d3dc5d276..5610cf71740e 100644
--- a/drivers/i3c/master/renesas-i3c.c
+++ b/drivers/i3c/master/renesas-i3c.c
@@ -835,7 +835,8 @@ static int renesas_i3c_priv_xfers(struct i3c_dev_desc *dev, struct i3c_priv_xfer
}
if (!i3c_xfers[i].rnw && i3c_xfers[i].len > 4) {
- i3c_writel_fifo(i3c->regs + NTDTBP0, cmd->tx_buf, cmd->len);
+ i3c_writel_fifo(i3c->regs + NTDTBP0, cmd->tx_buf, cmd->len,
+ I3C_FIFO_LITTLE_ENDIAN);
if (cmd->len > NTDTBP0_DEPTH * sizeof(u32))
renesas_set_bit(i3c->regs, NTIE, NTIE_TDBEIE0);
}
@@ -1021,7 +1022,8 @@ static irqreturn_t renesas_i3c_tx_isr(int irq, void *data)
/* Clear the Transmit Buffer Empty status flag. */
renesas_clear_bit(i3c->regs, NTST, NTST_TDBEF0);
} else {
- i3c_writel_fifo(i3c->regs + NTDTBP0, cmd->tx_buf, cmd->len);
+ i3c_writel_fifo(i3c->regs + NTDTBP0, cmd->tx_buf, cmd->len,
+ I3C_FIFO_LITTLE_ENDIAN);
}
}
@@ -1061,7 +1063,8 @@ static irqreturn_t renesas_i3c_resp_isr(int irq, void *data)
if (NDBSTLV0_RDBLV(renesas_readl(i3c->regs, NDBSTLV0)) && !cmd->err)
bytes_remaining = data_len - cmd->rx_count;
- i3c_readl_fifo(i3c->regs + NTDTBP0, cmd->rx_buf, bytes_remaining);
+ i3c_readl_fifo(i3c->regs + NTDTBP0, cmd->rx_buf, bytes_remaining,
+ I3C_FIFO_LITTLE_ENDIAN);
renesas_clear_bit(i3c->regs, NTIE, NTIE_RDBFIE0);
break;
default:
@@ -1203,7 +1206,8 @@ static irqreturn_t renesas_i3c_rx_isr(int irq, void *data)
cmd->i2c_bytes_left--;
} else {
read_bytes = NDBSTLV0_RDBLV(renesas_readl(i3c->regs, NDBSTLV0)) * sizeof(u32);
- i3c_readl_fifo(i3c->regs + NTDTBP0, cmd->rx_buf, read_bytes);
+ i3c_readl_fifo(i3c->regs + NTDTBP0, cmd->rx_buf, read_bytes,
+ I3C_FIFO_LITTLE_ENDIAN);
cmd->rx_count = read_bytes;
}
--
2.34.1Hi Manikanta,
kernel test robot noticed the following build warnings:
[auto build test WARNING on robh/for-next]
[also build test WARNING on linus/master arnd-asm-generic/master v6.17-rc7 next-20250924]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Manikanta-Guntupalli/dt-bindings-i3c-Add-AMD-I3C-master-controller-support/20250923-234944
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20250923154551.2112388-4-manikanta.guntupalli%40amd.com
patch subject: [PATCH V7 3/4] i3c: master: Add endianness support for i3c_readl_fifo() and i3c_writel_fifo()
config: mips-randconfig-r123-20250925 (https://download.01.org/0day-ci/archive/20250925/202509252022.QvbNmJil-lkp@intel.com/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project cafc064fc7a96b3979a023ddae1da2b499d6c954)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250925/202509252022.QvbNmJil-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202509252022.QvbNmJil-lkp@intel.com/
sparse warnings: (new ones prefixed by >>)
drivers/i3c/master/i3c-master-cdns.c: note: in included file:
>> drivers/i3c/master/../internals.h:53:25: sparse: sparse: incorrect type in argument 1 (different base types) @@ expected unsigned int [usertype] val @@ got restricted __be32 [usertype] @@
drivers/i3c/master/../internals.h:53:25: sparse: expected unsigned int [usertype] val
drivers/i3c/master/../internals.h:53:25: sparse: got restricted __be32 [usertype]
>> drivers/i3c/master/../internals.h:53:25: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *mem @@ got unsigned int * @@
drivers/i3c/master/../internals.h:53:25: sparse: expected void volatile [noderef] __iomem *mem
drivers/i3c/master/../internals.h:53:25: sparse: got unsigned int *
>> drivers/i3c/master/../internals.h:78:31: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got unsigned int * @@
drivers/i3c/master/../internals.h:78:31: sparse: expected void const volatile [noderef] __iomem *mem
drivers/i3c/master/../internals.h:78:31: sparse: got unsigned int *
>> drivers/i3c/master/../internals.h:78:31: sparse: sparse: cast to restricted __be32
>> drivers/i3c/master/../internals.h:78:31: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *mem @@ got unsigned int * @@
drivers/i3c/master/../internals.h:78:31: sparse: expected void const volatile [noderef] __iomem *mem
drivers/i3c/master/../internals.h:78:31: sparse: got unsigned int *
>> drivers/i3c/master/../internals.h:78:31: sparse: sparse: cast to restricted __be32
vim +53 drivers/i3c/master/../internals.h
31
32 /**
33 * i3c_writel_fifo - Write data buffer to 32bit FIFO
34 * @addr: FIFO Address to write to
35 * @buf: Pointer to the data bytes to write
36 * @nbytes: Number of bytes to write
37 * @endian: Endianness of FIFO write
38 */
39 static inline void i3c_writel_fifo(void __iomem *addr, const void *buf,
40 int nbytes, enum i3c_fifo_endian endian)
41 {
42 if (endian)
43 writesl_be(addr, buf, nbytes / 4);
44 else
45 writesl(addr, buf, nbytes / 4);
46
47 if (nbytes & 3) {
48 u32 tmp = 0;
49
50 memcpy(&tmp, buf + (nbytes & ~3), nbytes & 3);
51
52 if (endian)
> 53 writel_be(tmp, addr);
54 else
55 writel(tmp, addr);
56 }
57 }
58
59 /**
60 * i3c_readl_fifo - Read data buffer from 32bit FIFO
61 * @addr: FIFO Address to read from
62 * @buf: Pointer to the buffer to store read bytes
63 * @nbytes: Number of bytes to read
64 * @endian: Endianness of FIFO read
65 */
66 static inline void i3c_readl_fifo(const void __iomem *addr, void *buf,
67 int nbytes, enum i3c_fifo_endian endian)
68 {
69 if (endian)
70 readsl_be(addr, buf, nbytes / 4);
71 else
72 readsl(addr, buf, nbytes / 4);
73
74 if (nbytes & 3) {
75 u32 tmp;
76
77 if (endian)
> 78 tmp = readl_be(addr);
79 else
80 tmp = readl(addr);
81
82 memcpy(buf + (nbytes & ~3), &tmp, nbytes & 3);
83 }
84 }
85
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
On Tue, Sep 23, 2025, at 17:45, Manikanta Guntupalli wrote:
> /**
> * i3c_writel_fifo - Write data buffer to 32bit FIFO
> * @addr: FIFO Address to write to
> * @buf: Pointer to the data bytes to write
> * @nbytes: Number of bytes to write
> + * @endian: Endianness of FIFO write
> */
> static inline void i3c_writel_fifo(void __iomem *addr, const void *buf,
> - int nbytes)
> + int nbytes, enum i3c_fifo_endian endian)
> {
> - writesl(addr, buf, nbytes / 4);
> + if (endian)
> + writesl_be(addr, buf, nbytes / 4);
> + else
> + writesl(addr, buf, nbytes / 4);
> +
This seems counter-intuitive: a FIFO doesn't really have
an endianness, it is instead used to transfer a stream of
bytes, so if the device has a fixed endianess, the
FIFO still needs to be read using a plain writesl().
I see that your writesl_be() has an incorrect definition, which
would lead to the i3c_writel_fifo() function accidentally still
working if both the device and CPU use big-endian registers:
static inline void writesl_be(volatile void __iomem *addr,
const void *buffer,
unsigned int count)
{
if (count) {
const u32 *buf = buffer;
do {
__raw_writel((u32 __force)__cpu_to_be32(*buf), addr);
buf++;
} while (--count);
}
}
The __cpu_to_be32() call that you add here means that the
FIFO data is swapped on little-endian CPUs but not swapped
on big-endian ones. Compare this to the normal writesl()
function that never swaps because it writes a byte stream.
> if (nbytes & 3) {
> u32 tmp = 0;
>
> memcpy(&tmp, buf + (nbytes & ~3), nbytes & 3);
> - writel(tmp, addr);
> +
> + if (endian)
> + writel_be(tmp, addr);
> + else
> + writel(tmp, addr);
This bit however seems to fix a bug, but does so in a
confusing way. The way the FIFO registers usually deal
with excess bytes is to put them into the first bytes
of the FIFO register, so this should just be a
writesl(addr, &tmp, 1);
to write one set of four bytes into the FIFO without
endian-swapping.
Could it be that you are just trying to use a normal
i3c adapter with little-endian registers on a normal
big-endian machine but ran into this bug?
Arnd
On Tue, Sep 23, 2025 at 09:15:50PM +0530, Manikanta Guntupalli wrote:
> Add endianness handling to the FIFO access helpers i3c_readl_fifo() and
> i3c_writel_fifo(). This ensures correct data transfers on platforms where
> the FIFO registers are expected to be accessed in either big-endian or
> little-endian format.
>
> Update the Synopsys, Cadence, and Renesas I3C master controller drivers to
> pass the appropriate endianness argument to these helpers.
>
> Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> Changes since V7:
> This patch introduced in V7.
> ---
> drivers/i3c/internals.h | 35 +++++++++++++++++++++++-----
> drivers/i3c/master/dw-i3c-master.c | 9 ++++---
> drivers/i3c/master/i3c-master-cdns.c | 9 ++++---
> drivers/i3c/master/renesas-i3c.c | 12 ++++++----
> 4 files changed, 49 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/i3c/internals.h b/drivers/i3c/internals.h
> index 0d857cc68cc5..399bbf006dcd 100644
> --- a/drivers/i3c/internals.h
> +++ b/drivers/i3c/internals.h
> @@ -24,21 +24,35 @@ int i3c_dev_request_ibi_locked(struct i3c_dev_desc *dev,
> const struct i3c_ibi_setup *req);
> void i3c_dev_free_ibi_locked(struct i3c_dev_desc *dev);
>
> +enum i3c_fifo_endian {
> + I3C_FIFO_LITTLE_ENDIAN,
> + I3C_FIFO_BIG_ENDIAN,
> +};
> +
> /**
> * i3c_writel_fifo - Write data buffer to 32bit FIFO
> * @addr: FIFO Address to write to
> * @buf: Pointer to the data bytes to write
> * @nbytes: Number of bytes to write
> + * @endian: Endianness of FIFO write
> */
> static inline void i3c_writel_fifo(void __iomem *addr, const void *buf,
> - int nbytes)
> + int nbytes, enum i3c_fifo_endian endian)
> {
> - writesl(addr, buf, nbytes / 4);
> + if (endian)
> + writesl_be(addr, buf, nbytes / 4);
> + else
> + writesl(addr, buf, nbytes / 4);
> +
> if (nbytes & 3) {
> u32 tmp = 0;
>
> memcpy(&tmp, buf + (nbytes & ~3), nbytes & 3);
> - writel(tmp, addr);
> +
> + if (endian)
> + writel_be(tmp, addr);
> + else
> + writel(tmp, addr);
> }
> }
>
> @@ -47,15 +61,24 @@ static inline void i3c_writel_fifo(void __iomem *addr, const void *buf,
> * @addr: FIFO Address to read from
> * @buf: Pointer to the buffer to store read bytes
> * @nbytes: Number of bytes to read
> + * @endian: Endianness of FIFO read
> */
> static inline void i3c_readl_fifo(const void __iomem *addr, void *buf,
> - int nbytes)
> + int nbytes, enum i3c_fifo_endian endian)
> {
> - readsl(addr, buf, nbytes / 4);
> + if (endian)
> + readsl_be(addr, buf, nbytes / 4);
> + else
> + readsl(addr, buf, nbytes / 4);
> +
> if (nbytes & 3) {
> u32 tmp;
>
> - tmp = readl(addr);
> + if (endian)
> + tmp = readl_be(addr);
> + else
> + tmp = readl(addr);
> +
> memcpy(buf + (nbytes & ~3), &tmp, nbytes & 3);
> }
> }
> diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c
> index 974122b2d20e..5d723ac041c2 100644
> --- a/drivers/i3c/master/dw-i3c-master.c
> +++ b/drivers/i3c/master/dw-i3c-master.c
> @@ -337,19 +337,22 @@ static int dw_i3c_master_get_free_pos(struct dw_i3c_master *master)
> static void dw_i3c_master_wr_tx_fifo(struct dw_i3c_master *master,
> const u8 *bytes, int nbytes)
> {
> - i3c_writel_fifo(master->regs + RX_TX_DATA_PORT, bytes, nbytes);
> + i3c_writel_fifo(master->regs + RX_TX_DATA_PORT, bytes, nbytes,
> + I3C_FIFO_LITTLE_ENDIAN);
> }
>
> static void dw_i3c_master_read_rx_fifo(struct dw_i3c_master *master,
> u8 *bytes, int nbytes)
> {
> - i3c_readl_fifo(master->regs + RX_TX_DATA_PORT, bytes, nbytes);
> + i3c_readl_fifo(master->regs + RX_TX_DATA_PORT, bytes, nbytes,
> + I3C_FIFO_LITTLE_ENDIAN);
> }
>
> static void dw_i3c_master_read_ibi_fifo(struct dw_i3c_master *master,
> u8 *bytes, int nbytes)
> {
> - i3c_readl_fifo(master->regs + IBI_QUEUE_STATUS, bytes, nbytes);
> + i3c_readl_fifo(master->regs + IBI_QUEUE_STATUS, bytes, nbytes,
> + I3C_FIFO_LITTLE_ENDIAN);
> }
>
> static struct dw_i3c_xfer *
> diff --git a/drivers/i3c/master/i3c-master-cdns.c b/drivers/i3c/master/i3c-master-cdns.c
> index 97b151564d3d..de3b5e894b4b 100644
> --- a/drivers/i3c/master/i3c-master-cdns.c
> +++ b/drivers/i3c/master/i3c-master-cdns.c
> @@ -428,13 +428,15 @@ to_cdns_i3c_master(struct i3c_master_controller *master)
> static void cdns_i3c_master_wr_to_tx_fifo(struct cdns_i3c_master *master,
> const u8 *bytes, int nbytes)
> {
> - i3c_writel_fifo(master->regs + TX_FIFO, bytes, nbytes);
> + i3c_writel_fifo(master->regs + TX_FIFO, bytes, nbytes,
> + I3C_FIFO_LITTLE_ENDIAN);
> }
>
> static void cdns_i3c_master_rd_from_rx_fifo(struct cdns_i3c_master *master,
> u8 *bytes, int nbytes)
> {
> - i3c_readl_fifo(master->regs + RX_FIFO, bytes, nbytes);
> + i3c_readl_fifo(master->regs + RX_FIFO, bytes, nbytes,
> + I3C_FIFO_LITTLE_ENDIAN);
> }
>
> static bool cdns_i3c_master_supports_ccc_cmd(struct i3c_master_controller *m,
> @@ -1319,7 +1321,8 @@ static void cdns_i3c_master_handle_ibi(struct cdns_i3c_master *master,
> buf = slot->data;
>
> nbytes = IBIR_XFER_BYTES(ibir);
> - i3c_readl_fifo(master->regs + IBI_DATA_FIFO, buf, nbytes);
> + i3c_readl_fifo(master->regs + IBI_DATA_FIFO, buf, nbytes,
> + I3C_FIFO_LITTLE_ENDIAN);
>
> slot->len = min_t(unsigned int, IBIR_XFER_BYTES(ibir),
> dev->ibi->max_payload_len);
> diff --git a/drivers/i3c/master/renesas-i3c.c b/drivers/i3c/master/renesas-i3c.c
> index 174d3dc5d276..5610cf71740e 100644
> --- a/drivers/i3c/master/renesas-i3c.c
> +++ b/drivers/i3c/master/renesas-i3c.c
> @@ -835,7 +835,8 @@ static int renesas_i3c_priv_xfers(struct i3c_dev_desc *dev, struct i3c_priv_xfer
> }
>
> if (!i3c_xfers[i].rnw && i3c_xfers[i].len > 4) {
> - i3c_writel_fifo(i3c->regs + NTDTBP0, cmd->tx_buf, cmd->len);
> + i3c_writel_fifo(i3c->regs + NTDTBP0, cmd->tx_buf, cmd->len,
> + I3C_FIFO_LITTLE_ENDIAN);
> if (cmd->len > NTDTBP0_DEPTH * sizeof(u32))
> renesas_set_bit(i3c->regs, NTIE, NTIE_TDBEIE0);
> }
> @@ -1021,7 +1022,8 @@ static irqreturn_t renesas_i3c_tx_isr(int irq, void *data)
> /* Clear the Transmit Buffer Empty status flag. */
> renesas_clear_bit(i3c->regs, NTST, NTST_TDBEF0);
> } else {
> - i3c_writel_fifo(i3c->regs + NTDTBP0, cmd->tx_buf, cmd->len);
> + i3c_writel_fifo(i3c->regs + NTDTBP0, cmd->tx_buf, cmd->len,
> + I3C_FIFO_LITTLE_ENDIAN);
> }
> }
>
> @@ -1061,7 +1063,8 @@ static irqreturn_t renesas_i3c_resp_isr(int irq, void *data)
> if (NDBSTLV0_RDBLV(renesas_readl(i3c->regs, NDBSTLV0)) && !cmd->err)
> bytes_remaining = data_len - cmd->rx_count;
>
> - i3c_readl_fifo(i3c->regs + NTDTBP0, cmd->rx_buf, bytes_remaining);
> + i3c_readl_fifo(i3c->regs + NTDTBP0, cmd->rx_buf, bytes_remaining,
> + I3C_FIFO_LITTLE_ENDIAN);
> renesas_clear_bit(i3c->regs, NTIE, NTIE_RDBFIE0);
> break;
> default:
> @@ -1203,7 +1206,8 @@ static irqreturn_t renesas_i3c_rx_isr(int irq, void *data)
> cmd->i2c_bytes_left--;
> } else {
> read_bytes = NDBSTLV0_RDBLV(renesas_readl(i3c->regs, NDBSTLV0)) * sizeof(u32);
> - i3c_readl_fifo(i3c->regs + NTDTBP0, cmd->rx_buf, read_bytes);
> + i3c_readl_fifo(i3c->regs + NTDTBP0, cmd->rx_buf, read_bytes,
> + I3C_FIFO_LITTLE_ENDIAN);
> cmd->rx_count = read_bytes;
> }
>
> --
> 2.34.1
>
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