From: Biju Das <biju.das.jz@bp.renesas.com>
The GTIOC4{A,B} IOs are available on the carrier board's PMOD1_6A
connector. Enable the GPT on the carrier board by adding the GPT pinmux
and node on the carrier board dtsi file.
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
* No change.
v1->v2:
* Collected tags.
---
arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
index 08e814c03fa8..86df67e9230d 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
@@ -84,6 +84,14 @@ &can_transceiver1 {
};
#endif
+#if (!SW_LCD_EN) && (!SW_GPIO8_CAN0_STB)
+&gpt0 {
+ pinctrl-0 = <&gpt0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+#endif
+
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
@@ -125,6 +133,11 @@ can4_pins: can4 {
};
};
+ gpt0_pins: gpt0 {
+ pinmux = <RZG3E_PORT_PINMUX(5, 4, 10)>, /* GTIOC4A */
+ <RZG3E_PORT_PINMUX(5, 5, 10)>; /* GTIOC4B */
+ };
+
i2c0_pins: i2c0 {
pinmux = <RZG3E_PORT_PINMUX(D, 4, 4)>, /* SCL0 */
<RZG3E_PORT_PINMUX(D, 5, 4)>; /* SDA0 */
--
2.43.0