On 9/22/2025 1:25 PM, Ziyue Zhang wrote:
> Update the HAMOA-IOT-SOM device tree to enable PCIe 5 support. Add perst
> wake and clkreq sideband signals and required regulators in PCIe5
> controller and PHY device tree node.
>
> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
Reviewed-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
- Krishna Chaitanya.
> ---
> arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi | 40 +++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi
> index 1aead50b8920..0c8ae34c1f37 100644
> --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi
> +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi
> @@ -407,6 +407,23 @@ &pcie4_phy {
> status = "okay";
> };
>
> +&pcie5 {
> + perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
> +
> + pinctrl-0 = <&pcie5_default>;
> + pinctrl-names = "default";
> +
> + status = "okay";
> +};
> +
> +&pcie5_phy {
> + vdda-phy-supply = <&vreg_l3i_0p8>;
> + vdda-pll-supply = <&vreg_l3e_1p2>;
> +
> + status = "okay";
> +};
> +
> &pcie6a {
> perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
> wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
> @@ -477,6 +494,29 @@ wake-n-pins {
> };
> };
>
> + pcie5_default: pcie5-default-state {
> + clkreq-n-pins {
> + pins = "gpio150";
> + function = "pcie5_clk";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + perst-n-pins {
> + pins = "gpio149";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + wake-n-pins {
> + pins = "gpio151";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> pcie6a_default: pcie6a-default-state {
> clkreq-n-pins {
> pins = "gpio153";