Hi all,
This posting incorporates the following updates:
* Addressed Boris' feedbacks:
* Trimmed down changelogs to key points
* Clarified error messages
* Folded a one-liner helper
- Fixed typos
- Corrected header include ordering
* Collected Tony's review tag
Boris also commented on the heuristic, worth highlighting:
>> + * To tolerate this behavior, allow up to twice the expected
>> + * number of transactions (i.e., a 10-chunk image can take up to
>> + * 20 attempts).
>
> Looks quirky but ok, let's try it in practice first
...
> If this is part of normal operation, your send-max-2x-the-size heuristic might
> fail quickly here. I'd track the number of chunks it wants you to send and
> then set a per-chunk limit and when it reaches that limit, then cancel the
> transaction. Dunno, let's try the simple scheme first...
As the series continues to take shape, I hope this iteration can build
momentum towards the integration.
The branch is available here:
git://github.com/intel-staging/microcode.git staging_v6
Previous posting:
https://lore.kernel.org/lkml/20250823155214.17465-1-chang.seok.bae@intel.com/
Thanks,
Chang
Chang S. Bae (7):
x86/cpu/topology: Make primary thread mask available with SMP=n
x86/microcode: Introduce staging step to reduce late-loading time
x86/microcode/intel: Establish staging control logic
x86/microcode/intel: Define staging state struct
x86/microcode/intel: Implement staging handler
x86/microcode/intel: Support mailbox transfer
x86/microcode/intel: Enable staging when available
arch/x86/include/asm/msr-index.h | 9 +
arch/x86/include/asm/topology.h | 12 +-
arch/x86/kernel/cpu/microcode/core.c | 11 +
arch/x86/kernel/cpu/microcode/intel.c | 359 +++++++++++++++++++++++
arch/x86/kernel/cpu/microcode/internal.h | 4 +-
arch/x86/kernel/cpu/topology.c | 4 -
arch/x86/kernel/cpu/topology_common.c | 3 +
arch/x86/kernel/smpboot.c | 3 -
8 files changed, 391 insertions(+), 14 deletions(-)
base-commit: 835794d1ae4cb94b77f631f810018c286561181a
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2.48.1