phy: qcom: m31-eusb2: Update init sequence to set PHY_ENABLE

[PATCH] phy: qcom: m31-eusb2: Update init sequence to set PHY_ENABLE

Posted by Wesley Cheng 4 months, 3 weeks ago

From: Ronak Raheja <ronak.raheja@oss.qualcomm.com>

Certain platforms may not have the PHY_ENABLE bit set on power on reset.
Update the current sequence to explicitly write to enable the PHY_ENABLE
bit.  This ensures that regardless of the platform, the PHY is properly
enabled.

Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
---
 drivers/phy/qualcomm/phy-qcom-m31-eusb2.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c b/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c
index bf32572566c4..fbf5e999ca7a 100644
--- a/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c
+++ b/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c
@@ -25,6 +25,7 @@
 #define POR				BIT(1)
 
 #define USB_PHY_HS_PHY_CTRL_COMMON0	(0x54)
+#define PHY_ENABLE			BIT(0)
 #define SIDDQ_SEL			BIT(1)
 #define SIDDQ				BIT(2)
 #define FSEL				GENMASK(6, 4)
@@ -81,6 +82,7 @@ struct m31_eusb2_priv_data {
 static const struct m31_phy_tbl_entry m31_eusb2_setup_tbl[] = {
 	M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 1),
 	M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL5, POR, 1),
+	M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL_COMMON0, PHY_ENABLE, 1),
 	M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG1, PLL_EN, 1),
 	M31_EUSB_PHY_INIT_CFG(USB_PHY_FSEL_SEL, FSEL_SEL, 1),
 };

Re: [PATCH] phy: qcom: m31-eusb2: Update init sequence to set PHY_ENABLE

Posted by Vinod Koul 2 months, 2 weeks ago

On Fri, 19 Sep 2025 20:21:58 -0700, Wesley Cheng wrote:
> Certain platforms may not have the PHY_ENABLE bit set on power on reset.
> Update the current sequence to explicitly write to enable the PHY_ENABLE
> bit.  This ensures that regardless of the platform, the PHY is properly
> enabled.
> 
> 

Applied, thanks!

[1/1] phy: qcom: m31-eusb2: Update init sequence to set PHY_ENABLE
      commit: 7044ed6749c8a7d49e67b2f07f42da2f29d26be6

Best regards,
-- 
~Vinod

Re: [PATCH] phy: qcom: m31-eusb2: Update init sequence to set PHY_ENABLE

Posted by Neil Armstrong 2 months, 3 weeks ago

On 9/20/25 05:21, Wesley Cheng wrote:
> From: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> 
> Certain platforms may not have the PHY_ENABLE bit set on power on reset.
> Update the current sequence to explicitly write to enable the PHY_ENABLE
> bit.  This ensures that regardless of the platform, the PHY is properly
> enabled.
> 
> Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
> Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
> ---
>   drivers/phy/qualcomm/phy-qcom-m31-eusb2.c | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c b/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c
> index bf32572566c4..fbf5e999ca7a 100644
> --- a/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c
> +++ b/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c
> @@ -25,6 +25,7 @@
>   #define POR				BIT(1)
>   
>   #define USB_PHY_HS_PHY_CTRL_COMMON0	(0x54)
> +#define PHY_ENABLE			BIT(0)
>   #define SIDDQ_SEL			BIT(1)
>   #define SIDDQ				BIT(2)
>   #define FSEL				GENMASK(6, 4)
> @@ -81,6 +82,7 @@ struct m31_eusb2_priv_data {
>   static const struct m31_phy_tbl_entry m31_eusb2_setup_tbl[] = {
>   	M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 1),
>   	M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL5, POR, 1),
> +	M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL_COMMON0, PHY_ENABLE, 1),
>   	M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG1, PLL_EN, 1),
>   	M31_EUSB_PHY_INIT_CFG(USB_PHY_FSEL_SEL, FSEL_SEL, 1),
>   };

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>