On Fri, Sep 19, 2025 at 03:02:57PM +0800, Xu Yang wrote:
> Except default 24MHz clock, alternate 100MHz reference clock can be used
> as USB PHY reference clock too. Add "alt" clock and clock name.
Beside default 24MHz clock input, there is an optional additional 100Mhz
clock input 'alt' for USB PHY reference clock.
Frank
"Need emphase two clk inputs for this IP".
>
> Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> ---
> Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml
> index 22dd91591a09428214afaa4c9c8e37aae9bd8aba..268f86b04ce88cb81d2c06ee507fe0483d713f8f 100644
> --- a/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml
> @@ -27,11 +27,16 @@ properties:
> const: 0
>
> clocks:
> - maxItems: 1
> + minItems: 1
> + items:
> + - description: PHY configuration clock
> + - description: Alternate PHY reference clock
>
> clock-names:
> + minItems: 1
> items:
> - const: phy
> + - const: alt
>
> power-domains:
> maxItems: 1
>
> --
> 2.34.1
>