Add the offsets for a reset inside the dispcc on SM7150 SoC.
Signed-off-by: Jens Reidel <adrian@mainlining.org>
---
drivers/clk/qcom/dispcc-sm7150.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/clk/qcom/dispcc-sm7150.c b/drivers/clk/qcom/dispcc-sm7150.c
index bdfff246ed3fe08dea3647da9582e166cfbb96f4..0a7f6ec7a2a737c6f6f0484c71dd80f3dbf758b6 100644
--- a/drivers/clk/qcom/dispcc-sm7150.c
+++ b/drivers/clk/qcom/dispcc-sm7150.c
@@ -20,6 +20,7 @@
#include "clk-regmap-divider.h"
#include "common.h"
#include "gdsc.h"
+#include "reset.h"
enum {
DT_BI_TCXO,
@@ -951,6 +952,10 @@ static struct gdsc *dispcc_sm7150_gdscs[] = {
[MDSS_GDSC] = &mdss_gdsc,
};
+static const struct qcom_reset_map dispcc_sm7150_resets[] = {
+ [DISPCC_MDSS_CORE_BCR] = { 0x2000 },
+};
+
static const struct regmap_config dispcc_sm7150_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -965,6 +970,8 @@ static const struct qcom_cc_desc dispcc_sm7150_desc = {
.num_clks = ARRAY_SIZE(dispcc_sm7150_clocks),
.gdscs = dispcc_sm7150_gdscs,
.num_gdscs = ARRAY_SIZE(dispcc_sm7150_gdscs),
+ .resets = dispcc_sm7150_resets,
+ .num_resets = ARRAY_SIZE(dispcc_sm7150_resets),
};
static const struct of_device_id dispcc_sm7150_match_table[] = {
--
2.51.0