From: Chuan Liu <chuan.liu@amlogic.com>
The video clocks enci, encp, vdac and hdmitx share the same clock
source. Adding CLK_SET_RATE_PARENT to the mux may unintentionally change
the shared parent clock, which could affect other video clocks.
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
drivers/clk/meson/s4-peripherals.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peripherals.c
index aa500ea8ef9c..ba41fcd90588 100644
--- a/drivers/clk/meson/s4-peripherals.c
+++ b/drivers/clk/meson/s4-peripherals.c
@@ -1107,7 +1107,6 @@ static struct clk_regmap s4_cts_enci_sel = {
.ops = &clk_regmap_mux_ops,
.parent_hws = s4_cts_parents,
.num_parents = ARRAY_SIZE(s4_cts_parents),
- .flags = CLK_SET_RATE_PARENT,
},
};
@@ -1123,7 +1122,6 @@ static struct clk_regmap s4_cts_encp_sel = {
.ops = &clk_regmap_mux_ops,
.parent_hws = s4_cts_parents,
.num_parents = ARRAY_SIZE(s4_cts_parents),
- .flags = CLK_SET_RATE_PARENT,
},
};
@@ -1154,7 +1152,6 @@ static struct clk_regmap s4_cts_vdac_sel = {
.ops = &clk_regmap_mux_ops,
.parent_hws = s4_cts_parents,
.num_parents = ARRAY_SIZE(s4_cts_parents),
- .flags = CLK_SET_RATE_PARENT,
},
};
@@ -1185,7 +1182,6 @@ static struct clk_regmap s4_hdmi_tx_sel = {
.ops = &clk_regmap_mux_ops,
.parent_hws = s4_hdmi_tx_parents,
.num_parents = ARRAY_SIZE(s4_hdmi_tx_parents),
- .flags = CLK_SET_RATE_PARENT,
},
};
--
2.42.0