Rockchip RK3528 ships one PCIe Gen2x1 controller that operates in RC
mode only. The SoC doesn't provide a separate MSI controller, thus the
one integrated in designware PCIe IP must be used. This series documents
the PCIe controller in dt-binding and describes it in the SoC devicetree.
Radxa E20C board is used for testing, whose LAN GbE port is provided
through an RTL8111H chip connected to PCIe controller. Its devicetree
is adjusted to enable the controller, and IPERF3 shows the interface
runs at full-speed. A typical result looks like
[ ID] Interval Transfer Bitrate Retr
[ 5] 0.00-10.00 sec 1.10 GBytes 942 Mbits/sec 0 sender
[ 5] 0.00-10.01 sec 1.10 GBytes 941 Mbits/sec receiver
This series is based on next-20250917, thanks for your time and review.
Changed from v1
- Collect review tags
- SoC devicetree
- Drop redundant PCLK_PCIE_PHY clock for PCIe node
- Use 32-bit DBI address, adjust SoC ranges property and reorder nodes
- Align cells of reg and ranges properties
- board devicetree
- drop redundant pinconf pcie_reset_g
- Add missing vpcie3v3-supply
- Link to v1: https://lore.kernel.org/all/20250906135246.19398-1-ziyao@disroot.org/
Yao Zi (3):
dt-bindings: PCI: dwc: rockchip: Add RK3528 variant
arm64: dts: rockchip: Add PCIe Gen2x1 controller for RK3528
arm64: dts: rockchip: Enable PCIe controller on Radxa E20C
.../bindings/pci/rockchip-dw-pcie.yaml | 3 +
.../boot/dts/rockchip/rk3528-radxa-e20c.dts | 12 ++++
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 56 ++++++++++++++++++-
3 files changed, 70 insertions(+), 1 deletion(-)
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2.50.1