drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 115 +++--- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 8 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 43 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 428 ++++++++++++++--------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 12 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 6 +- drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 10 +- 10 files changed, 380 insertions(+), 248 deletions(-)
2 or more SSPPs and dual-DSI interface are need for super wide panel.
And 4 DSC are preferred for power optimal in this case due to width
limitation of SSPP and MDP clock rate constrain. This patch set
extends number of pipes to 4 and revise related mixer blending logic
to support quad pipe. All these changes depends on the virtual plane
feature to split a super wide drm plane horizontally into 2 or more sub
clip. Thus DMA of multiple SSPPs can share the effort of fetching the
whole drm plane.
The first pipe pair co-work with the first mixer pair to cover the left
half of screen and 2nd pair of pipes and mixers are for the right half
of screen. If a plane is only for the right half of screen, only one
or two of pipes in the 2nd pipe pair are valid, and no SSPP or mixer is
assinged for invalid pipe.
For those panel that does not require quad-pipe, only 1 or 2 pipes in
the 1st pipe pair will be used. There is no concept of right half of
screen.
For legacy non virtual plane mode, the first 1 or 2 pipes are used for
the single SSPP and its multi-rect mode.
Changes in v16:
- Rebase to latest branch msm-next-lumag.
- Fix IGT test failures.
- Drop patches that have been merged.
- Link to v15: https://lore.kernel.org/r/20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org
Changes in v15:
- Polish logic in sspp check and assignment.
- Link to v14: https://lore.kernel.org/r/20250801-v6-16-rc2-quad-pipe-upstream-v14-0-b626236f4c31@linaro.org
Changes in v14:
- Add patch to fix null pointer bug SSPP sharing, which is missed in
the last version.
- Polish single pipe check with removing loop.
- Polish logic of SSPP sharing test in dpu_plane_virtual_assign_resources()
- Polish argument of dpu_plane_virtual_assign_resources().
- Link to v13: https://lore.kernel.org/r/20250728-v6-16-rc2-quad-pipe-upstream-v13-0-954e4917fe4f@linaro.org
Changes in v13:
- Modify the SSPP assignment patch for sharing SSPP among planes in
quad-pipe case.
- Link to v12: https://lore.kernel.org/r/20250707-v6-16-rc2-quad-pipe-upstream-v12-0-67e3721e7d83@linaro.org
Changes in v12:
- Polish single pipe case detection in a plane. Add stage index check when
sharing SSPP with multi-rect mode in 2 planes.
- Abstract SSPP assignment in a stage into a function.
- Rebase to latest msm/msm-next.
- Link to v11: https://lore.kernel.org/r/20250603-v6-15-quad-pipe-upstream-v11-0-c3af7190613d@linaro.org
Changes in v11:
- Change function name from dpu_plane_check_single_pipe to
dpu_plane_get_single_pipe.
- Abstract SSPP assignment in stage into a function.
- Link to v10: https://lore.kernel.org/r/20250526-v6-15-quad-pipe-upstream-v10-0-5fed4f8897c4@linaro.org
Changes in v10:
- Drop changes in drm helper side, because num_lm == 0 does not lead to
any issue in the first call to dpu_plane_atomic_check_nosspp() with
latest repo. It is initialized properly right after the call in
drm_atomic_helper_check_planes(), thus the later plane splitting works
as expected.
- Rebase to latest msm-next branch.
- Fix PIPES_PER_STAGE to PIPES_PER_PLANE where handling all pipes, instead
of stages.
- Link to v9: https://lore.kernel.org/r/20250506-quad-pipe-upstream-v9-0-f7b273a8cc80@linaro.org
Changes in v9:
- Rebase to latest mainline and drop 3 patches as mainline already cover
the logic.
"Do not fix number of DSC"
"configure DSC per number in use"
"switch RM to use crtc_id rather than enc_id for allocation"
- Add a patch to check crtc before checking plane in drm framework.
- Add a patch to use dedicated WB number in an encoder to avoid regression.
- Revise the condition to decide quad-pipe topology.
- Link to v8: https://lore.kernel.org/r/20250303-sm8650-v6-14-hmd-deckard-mdss-quad-upstream-oldbootwrapper-36-prep-v8-0-eb5df105c807@linaro.org
Changes in v8:
- Fix looping pipes of a plane in _dpu_plane_color_fill()
- Improve pipe assignment with deleting pipes loop in stage.
- Define PIPES_PER_PLANE properly when it appears fisrt.
- rename lms_in_pair to lms_in_stage to avoid confusion.
- Add review tags.
- Link to v7: https://lore.kernel.org/r/20250226-sm8650-v6-14-hmd-deckard-mdss-quad-upstream-oldbootwrapper-36-prep-v7-0-8d5f5f426eb2@linaro.org
Changes in v7:
- Improve pipe assignment to avoid point to invalid memory.
- Define STAGES_PER_PLANE as 2 only when quad-pipe is introduced.
- Polish LM number when blending pipes with min() and pull up to caller func.
- Add review tags.
- Link to v6: https://lore.kernel.org/r/20250217-sm8650-v6-14-hmd-deckard-mdss-quad-upstream-oldbootwrapper-36-prep-v6-0-c11402574367@linaro.org
Changes in v6:
- Replace LM number with PP number to calculate PP number per encoder.
- Rebase to Linux v6.14-rc2.
- Add review tags.
- Link to v5: https://lore.kernel.org/r/20250118-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v5-0-9701a16340da@linaro.org
Changes in v5:
- Iterate SSPP flushing within the required mixer pair, instead of all
active mixers or specific mixer.
- Limit qaud-pipe usage case to SoC with 4 or more DSC engines and 2
interfaces case.
- Remove valid flag and use width for pipe validation.
- Polish commit messages and code comments.
- Link to v4: https://lore.kernel.org/r/20250116-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v4-0-74749c6eba33@linaro.org
Changes in v4:
- Restrict SSPP flushing to the required mixer, instead of all active mixers.
- Polish commit messages and code comments.
- Rebase to latest msm/drm-next branch.
- Move pipe checking patch to the top of patch set.
- Link to v3: https://lore.kernel.org/dri-devel/20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org
Changes in v3:
- Split change in trace into a separate patch.
- Rebase to latest msm-next branch.
- Reorder patch sequence to make sure valid flag is set in earlier patch
- Rectify rewrite patch to move logic change into other patch
- Polish commit messages and code comments.
- Link to v2: https://lore.kernel.org/dri-devel/20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org
Changes in v2:
- Revise the patch sequence with changing to 2 pipes topology first. Then
prepare for quad-pipe setup, then enable quad-pipe at last.
- Split DSI patches into other patch set.
- Link to v1: https://lore.kernel.org/all/20240829-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-8-v1-0-bdb05b4b5a2e@linaro.org
Signed-off-by: Jun Nie <jun.nie@linaro.org>
---
Jun Nie (10):
drm/msm/dpu: fix mixer number counter on allocation
drm/msm/dpu: bind correct pingpong for quad pipe
drm/msm/dpu: Add pipe as trace argument
drm/msm/dpu: handle pipes as array
drm/msm/dpu: split PIPES_PER_STAGE definition per plane and mixer
drm/msm/dpu: Use dedicated WB number definition
drm/msm/dpu: blend pipes per mixer pairs config
drm/msm/dpu: support SSPP assignment for quad-pipe case
drm/msm/dpu: support plane splitting in quad-pipe case
drm/msm/dpu: Enable quad-pipe for DSC and dual-DSI case
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 115 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 8 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 43 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 +
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 428 ++++++++++++++---------
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 12 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 6 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 10 +-
10 files changed, 380 insertions(+), 248 deletions(-)
---
base-commit: 01f31f83a125db48c058e1864cbfe877c086b6fb
change-id: 20250918-v6-16-rc2-quad-pipe-upstream-4-c871c0c93bc0
Best regards,
--
Jun Nie <jun.nie@linaro.org>
On Thu, Sep 18, 2025 at 09:28:52PM +0800, Jun Nie wrote: > 2 or more SSPPs and dual-DSI interface are need for super wide panel. > And 4 DSC are preferred for power optimal in this case due to width > limitation of SSPP and MDP clock rate constrain. This patch set > extends number of pipes to 4 and revise related mixer blending logic > to support quad pipe. All these changes depends on the virtual plane > feature to split a super wide drm plane horizontally into 2 or more sub > clip. Thus DMA of multiple SSPPs can share the effort of fetching the > whole drm plane. > > The first pipe pair co-work with the first mixer pair to cover the left > half of screen and 2nd pair of pipes and mixers are for the right half > of screen. If a plane is only for the right half of screen, only one > or two of pipes in the 2nd pipe pair are valid, and no SSPP or mixer is > assinged for invalid pipe. > > For those panel that does not require quad-pipe, only 1 or 2 pipes in > the 1st pipe pair will be used. There is no concept of right half of > screen. > > For legacy non virtual plane mode, the first 1 or 2 pipes are used for > the single SSPP and its multi-rect mode. > > Changes in v16: > - Rebase to latest branch msm-next-lumag. > - Fix IGT test failures. > - Drop patches that have been merged. > - Link to v15: https://lore.kernel.org/r/20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org Thanks. It's too invasive and too late for 6.18, but I've started the test run at https://gitlab.freedesktop.org/drm/msm/-/merge_requests/191 -- With best wishes Dmitry
On Fri, Sep 19, 2025 at 03:41:56AM +0300, Dmitry Baryshkov wrote: > On Thu, Sep 18, 2025 at 09:28:52PM +0800, Jun Nie wrote: > > 2 or more SSPPs and dual-DSI interface are need for super wide panel. > > And 4 DSC are preferred for power optimal in this case due to width > > limitation of SSPP and MDP clock rate constrain. This patch set > > extends number of pipes to 4 and revise related mixer blending logic > > to support quad pipe. All these changes depends on the virtual plane > > feature to split a super wide drm plane horizontally into 2 or more sub > > clip. Thus DMA of multiple SSPPs can share the effort of fetching the > > whole drm plane. > > > > The first pipe pair co-work with the first mixer pair to cover the left > > half of screen and 2nd pair of pipes and mixers are for the right half > > of screen. If a plane is only for the right half of screen, only one > > or two of pipes in the 2nd pipe pair are valid, and no SSPP or mixer is > > assinged for invalid pipe. > > > > For those panel that does not require quad-pipe, only 1 or 2 pipes in > > the 1st pipe pair will be used. There is no concept of right half of > > screen. > > > > For legacy non virtual plane mode, the first 1 or 2 pipes are used for > > the single SSPP and its multi-rect mode. > > > > Changes in v16: > > - Rebase to latest branch msm-next-lumag. > > - Fix IGT test failures. > > - Drop patches that have been merged. > > - Link to v15: https://lore.kernel.org/r/20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org > > Thanks. It's too invasive and too late for 6.18, but I've started the > test run at https://gitlab.freedesktop.org/drm/msm/-/merge_requests/191 JFYI: this has passed the IGT testing, so it will be picked up soon after 6.18-rc1. -- With best wishes Dmitry
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