The spi nor on imx8mm evk board works under SDR mode, and
driver use FlexSPIn_MCR0[RXCLKSRC] = 0x0 for SDR mode.
According to the datasheet, there is IO limitation on this chip,
the max frequency of such case is 66MHz, so add the limitation
here to align with datasheet.

Refer to 3.9.10 FlexSPI timing parameters on page 59.
https://www.nxp.com/docs/en/data-sheet/IMX8MMIEC.pdf

Fixes: fa1652340af8 ("arm64: dts: imx8mm-evk: Add flexspi support")
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
index b68954bcc383cfc799877ff64c5d9a59dd863907..bb57c1db7c64adb20c996bbc2e3996e1fde5b98a 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
@@ -47,7 +47,7 @@ flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
-		spi-max-frequency = <80000000>;
+		spi-max-frequency = <66000000>;
 		spi-tx-bus-width = <1>;
 		spi-rx-bus-width = <4>;
 	};

-- 
2.34.1

On Wed, Sep 17, 2025 at 04:42:29PM +0800, Haibo Chen wrote:
>The spi nor on imx8mm evk board works under SDR mode, and
>driver use FlexSPIn_MCR0[RXCLKSRC] = 0x0 for SDR mode.
>According to the datasheet, there is IO limitation on this chip,
>the max frequency of such case is 66MHz, so add the limitation
>here to align with datasheet.
>
>Refer to 3.9.10 FlexSPI timing parameters on page 59.
>https://www.nxp.com/docs/en/data-sheet/IMX8MMIEC.pdf

The SoC SDR mode max supports 66MHz, 133MHz. DDR mode max supports 33MHz and
66MHz. Saying the driver now only use RXCLKSRC 0 to restrict the
device tree to 66MHz is not that correct.

The SoC max frequency could be coded in driver per my understanding.

For the QSPI-NOR chip, the spi-max-frequency should represent the NOR chip
frequency. But that chip supports SDR/DDR, so a new property
spi-ddr-max-frequency, if we take spi-max-frequency as the max NOR
CHIP SDR mode frequency?

So if spi-max-frequency is the maximum NOR chip SDR frequency, the driver
should also be update dthat DDR mode is not supported as of now.

Just my thoughts.

Regards
Peng.

Hi,

On Thu Sep 18, 2025 at 11:01 AM CEST, Peng Fan wrote:
> On Wed, Sep 17, 2025 at 04:42:29PM +0800, Haibo Chen wrote:
> >The spi nor on imx8mm evk board works under SDR mode, and
> >driver use FlexSPIn_MCR0[RXCLKSRC] = 0x0 for SDR mode.
> >According to the datasheet, there is IO limitation on this chip,
> >the max frequency of such case is 66MHz, so add the limitation
> >here to align with datasheet.
> >
> >Refer to 3.9.10 FlexSPI timing parameters on page 59.
> >https://www.nxp.com/docs/en/data-sheet/IMX8MMIEC.pdf
>
> The SoC SDR mode max supports 66MHz, 133MHz. DDR mode max supports 33MHz and
> 66MHz. Saying the driver now only use RXCLKSRC 0 to restrict the
> device tree to 66MHz is not that correct.
>
> The SoC max frequency could be coded in driver per my understanding.

Yes that is correct. The spi-max-frequency property is for the
device, not the capabilities of the controller. I.e. the flash chip
on the board.

> For the QSPI-NOR chip, the spi-max-frequency should represent the NOR chip
> frequency. But that chip supports SDR/DDR, so a new property
> spi-ddr-max-frequency, if we take spi-max-frequency as the max NOR
> CHIP SDR mode frequency?

Which chip is it? I'm not sure that this is required because the
supported modes might be in the SFDP data and we just support the
8d8d8d mode backed by the JEDEC standard.

-michael

> So if spi-max-frequency is the maximum NOR chip SDR frequency, the driver
> should also be update dthat DDR mode is not supported as of now.
>
> Just my thoughts.
>
> Regards
> Peng.