flexspi define four mode for sample clock source selection.
Here is the list of modes:
mode 0: Dummy Read strobe generated by FlexSPI Controller and loopback
internally
mode 1: Dummy Read strobe generated by FlexSPI Controller and loopback
from DQS pad
mode 2: Reserved
mode 3: Flash provided Read strobe and input from DQS pad
In default, flexspi use mode 0 after reset. And for DTR mode, flexspi
only support 8D-8D-8D mode. For 8D-8D-8D mode, IC suggest to use mode 3,
otherwise read always get incorrect data.
For DTR mode, flexspi will automatically div 2 of the root clock
and output to device. the formula is:
device_clock = root_clock / (is_dtr ? 2 : 1)
So correct the clock rate setting for DTR mode to get the max
performance.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
drivers/spi/spi-nxp-fspi.c | 56 +++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 53 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index bd61f951d6befdb78cdd84d4531aab378a47c56f..d25679fafad7a94a7ea2a79d7e3da53f4939c9fa 100644
--- a/drivers/spi/spi-nxp-fspi.c
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -399,7 +399,8 @@ struct nxp_fspi {
struct mutex lock;
struct pm_qos_request pm_qos_req;
int selected;
-#define FSPI_NEED_INIT (1 << 0)
+#define FSPI_NEED_INIT BIT(0)
+#define FSPI_DTR_MODE BIT(1)
int flags;
};
@@ -655,6 +656,40 @@ static void nxp_fspi_clk_disable_unprep(struct nxp_fspi *f)
return;
}
+/*
+ * Sample Clock source selection for Flash Reading
+ * Four modes defined by fspi:
+ * mode 0: Dummy Read strobe generated by FlexSPI Controller
+ * and loopback internally
+ * mode 1: Dummy Read strobe generated by FlexSPI Controller
+ * and loopback from DQS pad
+ * mode 2: Reserved
+ * mode 3: Flash provided Read strobe and input from DQS pad
+ *
+ * fspi default use mode 0 after reset
+ */
+static void nxp_fspi_select_rx_sample_clk_source(struct nxp_fspi *f,
+ bool op_is_dtr)
+{
+ u32 reg;
+
+ /*
+ * For 8D-8D-8D mode, need to use mode 3 (Flash provided Read
+ * strobe and input from DQS pad), otherwise read operaton may
+ * meet issue.
+ * This mode require flash device connect the DQS pad on board.
+ * For other modes, still use mode 0, keep align with before.
+ * spi_nor_suspend will disable 8D-8D-8D mode, also need to
+ * change the mode back to mode 0.
+ */
+ reg = fspi_readl(f, f->iobase + FSPI_MCR0);
+ if (op_is_dtr)
+ reg |= FSPI_MCR0_RXCLKSRC(3);
+ else /*select mode 0 */
+ reg &= ~FSPI_MCR0_RXCLKSRC(3);
+ fspi_writel(f, reg, f->iobase + FSPI_MCR0);
+}
+
static void nxp_fspi_dll_calibration(struct nxp_fspi *f)
{
int ret;
@@ -736,15 +771,18 @@ static void nxp_fspi_dll_override(struct nxp_fspi *f)
static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi,
const struct spi_mem_op *op)
{
+ /* flexspi only support one DTR mode: 8D-8D-8D */
+ bool op_is_dtr = op->cmd.dtr && op->addr.dtr && op->dummy.dtr && op->data.dtr;
unsigned long rate = op->max_freq;
int ret;
uint64_t size_kb;
/*
* Return, if previously selected target device is same as current
- * requested target device.
+ * requested target device. Also the DTR or STR mode do not change.
*/
- if (f->selected == spi_get_chipselect(spi, 0))
+ if ((f->selected == spi_get_chipselect(spi, 0)) &&
+ (!!(f->flags & FSPI_DTR_MODE) == op_is_dtr))
return;
/* Reset FLSHxxCR0 registers */
@@ -761,6 +799,18 @@ static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi,
dev_dbg(f->dev, "Target device [CS:%x] selected\n", spi_get_chipselect(spi, 0));
+ nxp_fspi_select_rx_sample_clk_source(f, op_is_dtr);
+
+ if (op_is_dtr) {
+ f->flags |= FSPI_DTR_MODE;
+ /* For DTR mode, flexspi will default div 2 and output to device.
+ * so here to config the root clock to 2 * device rate.
+ */
+ rate = rate * 2;
+ } else {
+ f->flags &= ~FSPI_DTR_MODE;
+ }
+
nxp_fspi_clk_disable_unprep(f);
ret = clk_set_rate(f->clk, rate);
--
2.34.1On Wed, Sep 17, 2025 at 03:27:09PM +0800, Haibo Chen wrote:
> flexspi define four mode for sample clock source selection.
> Here is the list of modes:
> mode 0: Dummy Read strobe generated by FlexSPI Controller and loopback
> internally
> mode 1: Dummy Read strobe generated by FlexSPI Controller and loopback
> from DQS pad
> mode 2: Reserved
> mode 3: Flash provided Read strobe and input from DQS pad
>
> In default, flexspi use mode 0 after reset. And for DTR mode, flexspi
> only support 8D-8D-8D mode. For 8D-8D-8D mode, IC suggest to use mode 3,
> otherwise read always get incorrect data.
>
> For DTR mode, flexspi will automatically div 2 of the root clock
> and output to device. the formula is:
> device_clock = root_clock / (is_dtr ? 2 : 1)
> So correct the clock rate setting for DTR mode to get the max
> performance.
>
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> ---
> drivers/spi/spi-nxp-fspi.c | 56 +++++++++++++++++++++++++++++++++++++++++++---
> 1 file changed, 53 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
> index bd61f951d6befdb78cdd84d4531aab378a47c56f..d25679fafad7a94a7ea2a79d7e3da53f4939c9fa 100644
> --- a/drivers/spi/spi-nxp-fspi.c
> +++ b/drivers/spi/spi-nxp-fspi.c
> @@ -399,7 +399,8 @@ struct nxp_fspi {
> struct mutex lock;
> struct pm_qos_request pm_qos_req;
> int selected;
> -#define FSPI_NEED_INIT (1 << 0)
> +#define FSPI_NEED_INIT BIT(0)
> +#define FSPI_DTR_MODE BIT(1)
> int flags;
> };
>
> @@ -655,6 +656,40 @@ static void nxp_fspi_clk_disable_unprep(struct nxp_fspi *f)
> return;
> }
>
> +/*
> + * Sample Clock source selection for Flash Reading
> + * Four modes defined by fspi:
> + * mode 0: Dummy Read strobe generated by FlexSPI Controller
> + * and loopback internally
> + * mode 1: Dummy Read strobe generated by FlexSPI Controller
> + * and loopback from DQS pad
> + * mode 2: Reserved
> + * mode 3: Flash provided Read strobe and input from DQS pad
> + *
> + * fspi default use mode 0 after reset
> + */
> +static void nxp_fspi_select_rx_sample_clk_source(struct nxp_fspi *f,
> + bool op_is_dtr)
> +{
> + u32 reg;
> +
> + /*
> + * For 8D-8D-8D mode, need to use mode 3 (Flash provided Read
> + * strobe and input from DQS pad), otherwise read operaton may
> + * meet issue.
> + * This mode require flash device connect the DQS pad on board.
> + * For other modes, still use mode 0, keep align with before.
> + * spi_nor_suspend will disable 8D-8D-8D mode, also need to
> + * change the mode back to mode 0.
> + */
> + reg = fspi_readl(f, f->iobase + FSPI_MCR0);
> + if (op_is_dtr)
> + reg |= FSPI_MCR0_RXCLKSRC(3);
> + else /*select mode 0 */
> + reg &= ~FSPI_MCR0_RXCLKSRC(3);
> + fspi_writel(f, reg, f->iobase + FSPI_MCR0);
> +}
> +
> static void nxp_fspi_dll_calibration(struct nxp_fspi *f)
> {
> int ret;
> @@ -736,15 +771,18 @@ static void nxp_fspi_dll_override(struct nxp_fspi *f)
> static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi,
> const struct spi_mem_op *op)
> {
> + /* flexspi only support one DTR mode: 8D-8D-8D */
> + bool op_is_dtr = op->cmd.dtr && op->addr.dtr && op->dummy.dtr && op->data.dtr;
> unsigned long rate = op->max_freq;
> int ret;
> uint64_t size_kb;
>
> /*
> * Return, if previously selected target device is same as current
> - * requested target device.
> + * requested target device. Also the DTR or STR mode do not change.
> */
> - if (f->selected == spi_get_chipselect(spi, 0))
> + if ((f->selected == spi_get_chipselect(spi, 0)) &&
> + (!!(f->flags & FSPI_DTR_MODE) == op_is_dtr))
> return;
>
> /* Reset FLSHxxCR0 registers */
> @@ -761,6 +799,18 @@ static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi,
>
> dev_dbg(f->dev, "Target device [CS:%x] selected\n", spi_get_chipselect(spi, 0));
>
> + nxp_fspi_select_rx_sample_clk_source(f, op_is_dtr);
> +
> + if (op_is_dtr) {
> + f->flags |= FSPI_DTR_MODE;
> + /* For DTR mode, flexspi will default div 2 and output to device.
> + * so here to config the root clock to 2 * device rate.
> + */
Does it pass check patch? suppose multi-line comments is
/*
* For DTR ...
*/
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> + rate = rate * 2;
> + } else {
> + f->flags &= ~FSPI_DTR_MODE;
> + }
> +
> nxp_fspi_clk_disable_unprep(f);
>
> ret = clk_set_rate(f->clk, rate);
>
> --
> 2.34.1
>
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