SDHC1 on the GW702x SOM routes to a connector for use on a baseboard
and as such are defined in the baseboard device-trees.
Remove it from the gw702x SOM device-tree.
Fixes: 0d5b288c2110 ("arm64: dts: freescale: Add imx8mp-venice-gw7905-2x")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
.../dts/freescale/imx8mp-venice-gw702x.dtsi | 20 -------------------
.../dts/freescale/imx8mp-venice-gw72xx.dtsi | 11 ----------
2 files changed, 31 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi
index dba35b3394bc..de852ebff571 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi
@@ -403,15 +403,6 @@ &uart2 {
status = "okay";
};
-/* off-board */
-&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
- bus-width = <4>;
- non-removable;
- status = "okay";
-};
-
/* eMMC */
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
@@ -514,17 +505,6 @@ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
>;
};
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
- MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
- MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
- MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
- MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
- MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
- >;
- };
-
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
index cf747ec6fa16..76020ef89bf3 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
@@ -365,17 +365,6 @@ MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140
>;
};
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
- MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
- MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
- MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
- MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
- MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
- >;
- };
-
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
--
2.25.1