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[PATCH] spi: mt65xx: add dual and quad mode for standard spi device

Tim Kuo posted 1 patch 2 weeks, 2 days ago
There is a newer version of this series
drivers/spi/spi-mt65xx.c | 33 ++++++++++++++++++++++++++++++---
1 file changed, 30 insertions(+), 3 deletions(-)
[PATCH] spi: mt65xx: add dual and quad mode for standard spi device
Posted by Tim Kuo 2 weeks, 2 days ago 
From: "Tim Kuo" <Tim.Kuo@mediatek.com>

Mediatek SPI hardware natively supports dual and quad modes, and these
modes are already enabled for SPI flash devices under spi-mem framework
in MTK SPI controller spi-mt65xx. However, other SPI devices, such as
touch panels, are limited to single mode because spi-mt65xx lacks SPI
mode argument parsing from SPI framework for these SPI devices outside
spi-mem framework.

This patch adds dual and quad mode support for these SPI devices by
introducing a new API, mtk_spi_set_nbits, for SPI mode argument parsing.

Signed-off-by: Tim Kuo <Tim.Kuo@mediatek.com>
---
 drivers/spi/spi-mt65xx.c | 33 ++++++++++++++++++++++++++++++---
 1 file changed, 30 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c
index 8a3c00c3af42..591740805740 100644
--- a/drivers/spi/spi-mt65xx.c
+++ b/drivers/spi/spi-mt65xx.c
@@ -563,6 +563,27 @@ static void mtk_spi_setup_packet(struct spi_controller *host)
 	writel(reg_val, mdata->base + SPI_CFG1_REG);
 }
 
+inline u32 mtk_spi_set_nbit(u32 nbit)
+{
+	u32 ret = 0;
+
+	switch (nbit) {
+	case SPI_NBITS_SINGLE:
+		ret = 0x0;
+		break;
+	case SPI_NBITS_DUAL:
+		ret = 0x1;
+		break;
+	case SPI_NBITS_QUAD:
+		ret = 0x2;
+		break;
+	default:
+		pr_info("unknown spi nbit mode, use single mode!");
+		break;
+	}
+	return ret;
+}
+
 static void mtk_spi_enable_transfer(struct spi_controller *host)
 {
 	u32 cmd;
@@ -729,10 +750,16 @@ static int mtk_spi_transfer_one(struct spi_controller *host,
 
 	/* prepare xfer direction and duplex mode */
 	if (mdata->dev_comp->ipm_design) {
-		if (!xfer->tx_buf || !xfer->rx_buf) {
+		if (xfer->tx_buf && xfer->rx_buf) {
+			reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_EN;
+		} else if (xfer->tx_buf) {
+			reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;
+			reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_DIR;
+			reg_val |= mtk_spi_set_nbit(xfer->tx_nbits);
+		} else {
 			reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;
-			if (xfer->rx_buf)
-				reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR;
+			reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR;
+			reg_val |= mtk_spi_set_nbit(xfer->rx_nbits);
 		}
 		writel(reg_val, mdata->base + SPI_CFG3_IPM_REG);
 	}
-- 
2.45.2
Re: [PATCH] spi: mt65xx: add dual and quad mode for standard spi device
Posted by AngeloGioacchino Del Regno 2 weeks, 2 days ago 
Il 16/09/25 10:15, Tim Kuo ha scritto:
> From: "Tim Kuo" <Tim.Kuo@mediatek.com>
> 
> Mediatek SPI hardware natively supports dual and quad modes, and these
> modes are already enabled for SPI flash devices under spi-mem framework
> in MTK SPI controller spi-mt65xx. However, other SPI devices, such as
> touch panels, are limited to single mode because spi-mt65xx lacks SPI
> mode argument parsing from SPI framework for these SPI devices outside
> spi-mem framework.
> 
> This patch adds dual and quad mode support for these SPI devices by
> introducing a new API, mtk_spi_set_nbits, for SPI mode argument parsing.
> 
> Signed-off-by: Tim Kuo <Tim.Kuo@mediatek.com>
> ---
>   drivers/spi/spi-mt65xx.c | 33 ++++++++++++++++++++++++++++++---
>   1 file changed, 30 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c
> index 8a3c00c3af42..591740805740 100644
> --- a/drivers/spi/spi-mt65xx.c
> +++ b/drivers/spi/spi-mt65xx.c
> @@ -563,6 +563,27 @@ static void mtk_spi_setup_packet(struct spi_controller *host)
>   	writel(reg_val, mdata->base + SPI_CFG1_REG);
>   }
>   
> +inline u32 mtk_spi_set_nbit(u32 nbit)
> +{
> +	u32 ret = 0;

You don't need ret here.

> +
> +	switch (nbit) {

	default:
		pr_warn_once("Unknown nbit mode %u. Falling back to single mode\n",
			     nbit);
		fallthrough;
	case SPI_NBITS_SINGLE:
		return 0x0;
	case SPI_NBITS_DUAL:
		return 0x1;
	case SPI_NBITS_QUAD:
		return 0x2;

> +	case SPI_NBITS_SINGLE:
> +		ret = 0x0;
> +		break;
> +	case SPI_NBITS_DUAL:
> +		ret = 0x1;
> +		break;
> +	case SPI_NBITS_QUAD:
> +		ret = 0x2;
> +		break;
> +	default:
> +		pr_info("unknown spi nbit mode, use single mode!");
> +		break;
> +	}
> +	return ret;
> +}
> +
>   static void mtk_spi_enable_transfer(struct spi_controller *host)
>   {
>   	u32 cmd;
> @@ -729,10 +750,16 @@ static int mtk_spi_transfer_one(struct spi_controller *host,
>   
>   	/* prepare xfer direction and duplex mode */
>   	if (mdata->dev_comp->ipm_design) {
> -		if (!xfer->tx_buf || !xfer->rx_buf) {
> +		if (xfer->tx_buf && xfer->rx_buf) {
> +			reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_EN;
> +		} else if (xfer->tx_buf) {
> +			reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;
> +			reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_DIR;
> +			reg_val |= mtk_spi_set_nbit(xfer->tx_nbits);
> +		} else {
>   			reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;
> -			if (xfer->rx_buf)
> -				reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR;
> +			reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR;
> +			reg_val |= mtk_spi_set_nbit(xfer->rx_nbits);
>   		}
>   		writel(reg_val, mdata->base + SPI_CFG3_IPM_REG);
>   	}

Everything else LGTM. So, after adding the requested changes

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Patchew 2.1-devel-b67e4c2

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