On i.MX, PCIe has two reference clock inputs: one from the internal PLL
and one from an external clock source. Only one needs to be used,
depending on the board design. Add the external reference clock source
for reference clock.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index ca5f2970f217..6be45abe6e52 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -219,7 +219,12 @@ allOf:
             - const: pcie_bus
             - const: pcie_phy
             - const: pcie_aux
-            - const: ref
+            - description: PCIe reference clock.
+              oneOf:
+                - description: The controller has two reference clock
+                    inputs, internal system PLL and external clock
+                    source. Only one needs to be used.
+                  enum: [ref, extref]
 
 unevaluatedProperties: false
 
-- 
2.37.1

On Mon, Sep 15, 2025 at 11:53:47AM +0800, Richard Zhu wrote:
> On i.MX, PCIe has two reference clock inputs: one from the internal PLL
> and one from an external clock source. Only one needs to be used,
> depending on the board design. Add the external reference clock source
> for reference clock.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> ---
>  Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> index ca5f2970f217..6be45abe6e52 100644
> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> @@ -219,7 +219,12 @@ allOf:
>              - const: pcie_bus
>              - const: pcie_phy
>              - const: pcie_aux
> -            - const: ref
> +            - description: PCIe reference clock.
> +              oneOf:
> +                - description: The controller has two reference clock
> +                    inputs, internal system PLL and external clock
> +                    source. Only one needs to be used.
> +                  enum: [ref, extref]

This seems wrong to me. There's still only 1 ref input to the PCIe 
block. If you had 10 possible choices for the ref clock source, would 
you add 10 clock names here? No!

Can't you detect what the parent clock is for the 'ref' clock? and 
configure the GPR register appropriately. Or that mux should be modeled 
as a clock provider.

Rob

On Mon, Sep 22, 2025 at 10:50:54AM -0500, Rob Herring wrote:
> On Mon, Sep 15, 2025 at 11:53:47AM +0800, Richard Zhu wrote:
> > On i.MX, PCIe has two reference clock inputs: one from the internal PLL
> > and one from an external clock source. Only one needs to be used,
> > depending on the board design. Add the external reference clock source
> > for reference clock.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > Reviewed-by: Frank Li <Frank.Li@nxp.com>
> > ---
> >  Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 7 ++++++-
> >  1 file changed, 6 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > index ca5f2970f217..6be45abe6e52 100644
> > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > @@ -219,7 +219,12 @@ allOf:
> >              - const: pcie_bus
> >              - const: pcie_phy
> >              - const: pcie_aux
> > -            - const: ref
> > +            - description: PCIe reference clock.
> > +              oneOf:
> > +                - description: The controller has two reference clock
> > +                    inputs, internal system PLL and external clock
> > +                    source. Only one needs to be used.
> > +                  enum: [ref, extref]
>
> This seems wrong to me. There's still only 1 ref input to the PCIe
> block. If you had 10 possible choices for the ref clock source, would
> you add 10 clock names here? No!
>
> Can't you detect what the parent clock is for the 'ref' clock?

In include/linux/clk.h, I have not found any API to get clk providor's
information. let me know if I missed it.

> and
> configure the GPR register appropriately. Or that mux should be modeled
> as a clock provider.

The mux is inside PCIe controller IP. Similar case in S32 RTC, which have
4 clk inputs and mux is inside IP.

https://lore.kernel.org/all/20241104152934.GA129622-robh@kernel.org/

We met many similar cases. Actually s32 rtc's first version modeled as
clock provider, but this way is rejected because no clock output.

Frank

>
> Rob