Add and enable all available QUP SEs on this board, allowing I2C, SPI and
UART functions from the 40-Pin GPIO header to work.

Signed-off-by: Xilin Wu <sophon@radxa.com>

---

This change depends on the following patch series:
https://lore.kernel.org/all/20250911043256.3523057-1-viken.dadhaniya@oss.qualcomm.com/
---
 .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts     | 66 ++++++++++++++++++++++
 1 file changed, 66 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
index 85465702279efb7ab324baea0663bdbdbd5fb5ac..d30cddfc3eff07237c7e3480a5d42b29091d87d6 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
@@ -432,6 +432,14 @@ &gcc {
 			   <GCC_WPSS_RSCP_CLK>;
 };
 
+&gpi_dma0 {
+	status = "okay";
+};
+
+&gpi_dma1 {
+	status = "okay";
+};
+
 &gpu {
 	status = "okay";
 };
@@ -440,6 +448,40 @@ &gpu_zap_shader {
 	firmware-name = "qcom/qcs6490/a660_zap.mbn";
 };
 
+/* Pin 13, 15 in GPIO header */
+&i2c0 {
+	qcom,enable-gsi-dma;
+	status = "okay";
+};
+
+/* Pin 27, 28 in GPIO header */
+&i2c2 {
+	qcom,enable-gsi-dma;
+	status = "okay";
+};
+
+/* Pin 3, 5 in GPIO header */
+&i2c6 {
+	qcom,enable-gsi-dma;
+	status = "okay";
+};
+
+&i2c10 {
+	qcom,enable-gsi-dma;
+	status = "okay";
+
+	rtc: rtc@68 {
+		compatible = "st,m41t11";
+		reg = <0x68>;
+	};
+};
+
+/* External touchscreen */
+&i2c13 {
+	qcom,enable-gsi-dma;
+	status = "okay";
+};
+
 &lpass_audiocc {
 	compatible = "qcom,qcm6490-lpassaudiocc";
 	/delete-property/ power-domains;
@@ -624,6 +666,12 @@ spi_flash: flash@0 {
 };
 
 &qupv3_id_0 {
+	firmware-name = "qcom/qcm6490/qupv3fw.elf";
+	status = "okay";
+};
+
+&qupv3_id_1 {
+	firmware-name = "qcom/qcm6490/qupv3fw.elf";
 	status = "okay";
 };
 
@@ -702,6 +750,24 @@ platform {
 	};
 };
 
+/* Pin 11, 29, 31, 32 in GPIO header */
+&spi7 {
+	qcom,enable-gsi-dma;
+	status = "okay";
+};
+
+/* Pin 19, 21, 23, 24, 26 in GPIO header */
+&spi12 {
+	qcom,enable-gsi-dma;
+	status = "okay";
+};
+
+/* Pin 22, 33, 36, 37 in GPIO header */
+&spi14 {
+	qcom,enable-gsi-dma;
+	status = "okay";
+};
+
 &swr0 {
 	status = "okay";
 

-- 
2.51.0

On 14/09/2025 17:57, Xilin Wu wrote:
> Add and enable all available QUP SEs on this board, allowing I2C, SPI and
> UART functions from the 40-Pin GPIO header to work.
> 
> Signed-off-by: Xilin Wu <sophon@radxa.com>
> 
> ---
> 
> This change depends on the following patch series:
> https://lore.kernel.org/all/20250911043256.3523057-1-viken.dadhaniya@oss.qualcomm.com/


No, why? It does not. If your DTS depends on drivers it's a mistake to fix.

Fix dependency or squash the patches.



Best regards,
Krzysztof

On 9/14/25 7:36 PM, Krzysztof Kozlowski wrote:
> On 14/09/2025 17:57, Xilin Wu wrote:
>> Add and enable all available QUP SEs on this board, allowing I2C, SPI and
>> UART functions from the 40-Pin GPIO header to work.
>>
>> Signed-off-by: Xilin Wu <sophon@radxa.com>
>>
>> ---
>>
>> This change depends on the following patch series:
>> https://lore.kernel.org/all/20250911043256.3523057-1-viken.dadhaniya@oss.qualcomm.com/
> 
> 
> No, why? It does not. If your DTS depends on drivers it's a mistake to fix.
> 
> Fix dependency or squash the patches.

That series also includes bindings changes

Konrad

On 15/09/2025 09:13, Konrad Dybcio wrote:
> On 9/14/25 7:36 PM, Krzysztof Kozlowski wrote:
>> On 14/09/2025 17:57, Xilin Wu wrote:
>>> Add and enable all available QUP SEs on this board, allowing I2C, SPI and
>>> UART functions from the 40-Pin GPIO header to work.
>>>
>>> Signed-off-by: Xilin Wu <sophon@radxa.com>
>>>
>>> ---
>>>
>>> This change depends on the following patch series:
>>> https://lore.kernel.org/all/20250911043256.3523057-1-viken.dadhaniya@oss.qualcomm.com/
>>
>>
>> No, why? It does not. If your DTS depends on drivers it's a mistake to fix.
>>
>> Fix dependency or squash the patches.
> 
> That series also includes bindings changes

So how does this depends on the bindings? What it the exact dependency
that you need to wait one cycle? Cannot be merged to next the same time?

That's a warning sign... and I really do not understand how new board
depends on the bindings.

Best regards,
Krzysztof