From: Drew Fustini <dfustini@tenstorrent.com>
Add device tree source describing the Tenstorrent Blackhole A0 SoC and
the Blackhole P100 and P150 PCIe cards. There are no differences between
the P100 and P150 cards from the perspective of an OS kernel like Linux
running on the X280 cores.
Link: https://github.com/tenstorrent/tt-isa-documentation/blob/main/BlackholeA0/
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
MAINTAINERS | 1 +
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/tenstorrent/Makefile | 2 +
.../boot/dts/tenstorrent/blackhole-a0-card.dts | 14 +++
arch/riscv/boot/dts/tenstorrent/blackhole-a0.dtsi | 112 +++++++++++++++++++++
5 files changed, 130 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index f2cb2aae8d66d21bf5c13b16b3b1d8fdc98b9462..20605d7530a6d19e928709647ea91a9cf7913ee7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -21748,6 +21748,7 @@ L: linux-riscv@lists.infradead.org
S: Maintained
T: git https://github.com/tenstorrent/linux.git
F: Documentation/devicetree/bindings/riscv/tenstorrent.yaml
+F: arch/riscv/boot/dts/tenstorrent/
RISC-V THEAD SoC SUPPORT
M: Drew Fustini <fustini@kernel.org>
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index 3b99e91efa25be2d6ca5bc173342c24a72f87187..0624199867065dbb5eb62d660f950b4aa3a7abd7 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -8,4 +8,5 @@ subdir-y += sifive
subdir-y += sophgo
subdir-y += spacemit
subdir-y += starfive
+subdir-y += tenstorrent
subdir-y += thead
diff --git a/arch/riscv/boot/dts/tenstorrent/Makefile b/arch/riscv/boot/dts/tenstorrent/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..009510bea6c8e558bda70850a7f8490b23bffdea
--- /dev/null
+++ b/arch/riscv/boot/dts/tenstorrent/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_TENSTORRENT) += blackhole-a0-card.dtb
diff --git a/arch/riscv/boot/dts/tenstorrent/blackhole-a0-card.dts b/arch/riscv/boot/dts/tenstorrent/blackhole-a0-card.dts
new file mode 100644
index 0000000000000000000000000000000000000000..b2b08023643a2cebd4f924579024290bb355c9b3
--- /dev/null
+++ b/arch/riscv/boot/dts/tenstorrent/blackhole-a0-card.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/dts-v1/;
+
+#include "blackhole-a0.dtsi"
+
+/ {
+ model = "Tenstorrent Blackhole A0 SoC PCIe card";
+ compatible = "tenstorrent,blackhole-a0-card", "tenstorrent,blackhole-a0";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x4000 0x30000000 0x1 0x00000000>;
+ };
+};
diff --git a/arch/riscv/boot/dts/tenstorrent/blackhole-a0.dtsi b/arch/riscv/boot/dts/tenstorrent/blackhole-a0.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..517b6442ff0fe61659069e29318ad3f01bc504e2
--- /dev/null
+++ b/arch/riscv/boot/dts/tenstorrent/blackhole-a0.dtsi
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// Copyright 2025 Tenstorrent AI ULC
+/dts-v1/;
+
+/ {
+ compatible = "tenstorrent,blackhole-a0";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ timebase-frequency = <50000000>;
+
+ cpu@0 {
+ compatible = "sifive,x280", "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ reg = <0>;
+ mmu-type = "riscv,sv57";
+ riscv,isa = "rv64imafdcv_zicsr_zifencei_zfh_zba_zbb_sscofpmf";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
+ "zifencei", "zfh", "zba", "zbb", "sscofpmf";
+ riscv,cboz-block-size = <0x40>;
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu@1 {
+ compatible = "sifive,x280", "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ reg = <1>;
+ mmu-type = "riscv,sv57";
+ riscv,isa = "rv64imafdcv_zicsr_zifencei_zfh_zba_zbb_sscofpmf";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
+ "zifencei", "zfh", "zba", "zbb", "sscofpmf";
+ riscv,cboz-block-size = <0x40>;
+ cpu1_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu@2 {
+ compatible = "sifive,x280", "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ reg = <2>;
+ mmu-type = "riscv,sv57";
+ riscv,isa = "rv64imafdcv_zicsr_zifencei_zfh_zba_zbb_sscofpmf";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
+ "zifencei", "zfh", "zba", "zbb", "sscofpmf";
+ riscv,cboz-block-size = <0x40>;
+ cpu2_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu@3 {
+ compatible = "sifive,x280", "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ reg = <3>;
+ mmu-type = "riscv,sv57";
+ riscv,isa-base = "rv64i";
+ riscv,isa = "rv64imafdcv_zicsr_zifencei_zfh_zba_zbb_sscofpmf";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
+ "zifencei", "zfh", "zba", "zbb", "sscofpmf";
+ riscv,cboz-block-size = <0x40>;
+ cpu3_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ clint0: timer@2000000 {
+ compatible = "tenstorrent,blackhole-a0-clint", "sifive,clint0";
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ interrupts-extended = <&cpu0_intc 0x3>, <&cpu0_intc 0x7>,
+ <&cpu1_intc 0x3>, <&cpu1_intc 0x7>,
+ <&cpu2_intc 0x3>, <&cpu2_intc 0x7>,
+ <&cpu3_intc 0x3>, <&cpu3_intc 0x7>;
+ };
+
+ plic0: interrupt-controller@c000000 {
+ compatible = "tenstorrent,blackhole-a0-plic", "sifive,plic-1.0.0";
+ reg = <0x0 0x0c000000 0x0 0x04000000>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+ <&cpu1_intc 11>, <&cpu1_intc 9>,
+ <&cpu2_intc 11>, <&cpu2_intc 9>,
+ <&cpu3_intc 11>, <&cpu3_intc 9>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ riscv,ndev = <128>;
+ };
+ };
+};
--
2.34.1On Sat, Sep 13, 2025 at 02:31:05PM -0700, Drew Fustini wrote:
> new file mode 100644
> index 0000000000000000000000000000000000000000..b2b08023643a2cebd4f924579024290bb355c9b3
> --- /dev/null
> +++ b/arch/riscv/boot/dts/tenstorrent/blackhole-a0-card.dts
> @@ -0,0 +1,14 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/dts-v1/;
> +
> +#include "blackhole-a0.dtsi"
> +
> +/ {
> + model = "Tenstorrent Blackhole A0 SoC PCIe card";
> + compatible = "tenstorrent,blackhole-a0-card", "tenstorrent,blackhole-a0";
> +
> + memory@0 {
> + device_type = "memory";
> + reg = <0x4000 0x30000000 0x1 0x00000000>;
This isn't at address zero as the node address claims.
> + };
> +};
> diff --git a/arch/riscv/boot/dts/tenstorrent/blackhole-a0.dtsi b/arch/riscv/boot/dts/tenstorrent/blackhole-a0.dtsi
> new file mode 100644
> index 0000000000000000000000000000000000000000..517b6442ff0fe61659069e29318ad3f01bc504e2
> --- /dev/null
> +++ b/arch/riscv/boot/dts/tenstorrent/blackhole-a0.dtsi
> @@ -0,0 +1,112 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +// Copyright 2025 Tenstorrent AI ULC
> +/dts-v1/;
> +
> +/ {
> + compatible = "tenstorrent,blackhole-a0";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <0x1>;
> + #size-cells = <0x0>;
> + timebase-frequency = <50000000>;
> +
> + cpu@0 {
> + compatible = "sifive,x280", "sifive,rocket0", "riscv";
> + device_type = "cpu";
> + reg = <0>;
> + mmu-type = "riscv,sv57";
> + riscv,isa = "rv64imafdcv_zicsr_zifencei_zfh_zba_zbb_sscofpmf";
What's the benefit of retaining this property?
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
> + "zifencei", "zfh", "zba", "zbb", "sscofpmf";
> + riscv,cboz-block-size = <0x40>;
cboz block size, but no zicboz in your extensions list?
On Mon, Sep 15, 2025 at 05:47:08PM +0100, Conor Dooley wrote:
> On Sat, Sep 13, 2025 at 02:31:05PM -0700, Drew Fustini wrote:
> > new file mode 100644
> > index 0000000000000000000000000000000000000000..b2b08023643a2cebd4f924579024290bb355c9b3
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/tenstorrent/blackhole-a0-card.dts
> > @@ -0,0 +1,14 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/dts-v1/;
> > +
> > +#include "blackhole-a0.dtsi"
> > +
> > +/ {
> > + model = "Tenstorrent Blackhole A0 SoC PCIe card";
> > + compatible = "tenstorrent,blackhole-a0-card", "tenstorrent,blackhole-a0";
> > +
> > + memory@0 {
> > + device_type = "memory";
> > + reg = <0x4000 0x30000000 0x1 0x00000000>;
>
> This isn't at address zero as the node address claims.
Thanks, I'll fix the unit address.
>
> > + };
> > +};
> > diff --git a/arch/riscv/boot/dts/tenstorrent/blackhole-a0.dtsi b/arch/riscv/boot/dts/tenstorrent/blackhole-a0.dtsi
> > new file mode 100644
> > index 0000000000000000000000000000000000000000..517b6442ff0fe61659069e29318ad3f01bc504e2
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/tenstorrent/blackhole-a0.dtsi
> > @@ -0,0 +1,112 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +// Copyright 2025 Tenstorrent AI ULC
> > +/dts-v1/;
> > +
> > +/ {
> > + compatible = "tenstorrent,blackhole-a0";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + cpus {
> > + #address-cells = <0x1>;
> > + #size-cells = <0x0>;
> > + timebase-frequency = <50000000>;
> > +
> > + cpu@0 {
> > + compatible = "sifive,x280", "sifive,rocket0", "riscv";
> > + device_type = "cpu";
> > + reg = <0>;
> > + mmu-type = "riscv,sv57";
>
> > + riscv,isa = "rv64imafdcv_zicsr_zifencei_zfh_zba_zbb_sscofpmf";
>
> What's the benefit of retaining this property?
Nothing depends on the legacy isa property so I'll drop it.
>
> > + riscv,isa-base = "rv64i";
> > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr",
> > + "zifencei", "zfh", "zba", "zbb", "sscofpmf";
> > + riscv,cboz-block-size = <0x40>;
>
> cboz block size, but no zicboz in your extensions list?
My mistake, the core does not have CBO so I'll drop this property.
Thanks,
Drew
On 15/09/2025 18:52, Drew Fustini wrote:
> On Mon, Sep 15, 2025 at 05:47:08PM +0100, Conor Dooley wrote:
>> On Sat, Sep 13, 2025 at 02:31:05PM -0700, Drew Fustini wrote:
>>> new file mode 100644
>>> index 0000000000000000000000000000000000000000..b2b08023643a2cebd4f924579024290bb355c9b3
>>> --- /dev/null
>>> +++ b/arch/riscv/boot/dts/tenstorrent/blackhole-a0-card.dts
>>> @@ -0,0 +1,14 @@
>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>> +/dts-v1/;
>>> +
>>> +#include "blackhole-a0.dtsi"
>>> +
>>> +/ {
>>> + model = "Tenstorrent Blackhole A0 SoC PCIe card";
>>> + compatible = "tenstorrent,blackhole-a0-card", "tenstorrent,blackhole-a0";
>>> +
>>> + memory@0 {
>>> + device_type = "memory";
>>> + reg = <0x4000 0x30000000 0x1 0x00000000>;
>>
>> This isn't at address zero as the node address claims.
>
> Thanks, I'll fix the unit address.
Is it time to just assume any dtc can handle a 64bit number?
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
https://www.codethink.co.uk/privacy.html
On Tue, Sep 16, 2025 at 02:56:05PM +0100, Ben Dooks wrote:
> On 15/09/2025 18:52, Drew Fustini wrote:
> > On Mon, Sep 15, 2025 at 05:47:08PM +0100, Conor Dooley wrote:
> > > On Sat, Sep 13, 2025 at 02:31:05PM -0700, Drew Fustini wrote:
> > > > new file mode 100644
> > > > index 0000000000000000000000000000000000000000..b2b08023643a2cebd4f924579024290bb355c9b3
> > > > --- /dev/null
> > > > +++ b/arch/riscv/boot/dts/tenstorrent/blackhole-a0-card.dts
> > > > @@ -0,0 +1,14 @@
> > > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > > > +/dts-v1/;
> > > > +
> > > > +#include "blackhole-a0.dtsi"
> > > > +
> > > > +/ {
> > > > + model = "Tenstorrent Blackhole A0 SoC PCIe card";
> > > > + compatible = "tenstorrent,blackhole-a0-card", "tenstorrent,blackhole-a0";
> > > > +
> > > > + memory@0 {
> > > > + device_type = "memory";
> > > > + reg = <0x4000 0x30000000 0x1 0x00000000>;
> > >
> > > This isn't at address zero as the node address claims.
> >
> > Thanks, I'll fix the unit address.
>
> Is it time to just assume any dtc can handle a 64bit number?
Is it not valid for me to use the 64 bit hex number in the unit address?
I changed it to memory@400030000000 and 'W=1 dtbs_check' did not
complain. Am I doing something wrong?
-------------------------------------------------
$ git diff
diff --git a/arch/riscv/boot/dts/tenstorrent/blackhole-a0-card.dts b/arch/riscv/boot/dts/tenstorrent/blackhole-a0-card.dts
index b2b08023643a..7963712b53ea 100644
--- a/arch/riscv/boot/dts/tenstorrent/blackhole-a0-card.dts
+++ b/arch/riscv/boot/dts/tenstorrent/blackhole-a0-card.dts
@@ -7,7 +7,7 @@ / {
model = "Tenstorrent Blackhole A0 SoC PCIe card";
compatible = "tenstorrent,blackhole-a0-card", "tenstorrent,blackhole-a0";
- memory@0 {
+ memory@400030000000 {
device_type = "memory";
reg = <0x4000 0x30000000 0x1 0x00000000>;
};
$ make W=1 ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- -j32 dtbs_check
DTC [C] arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dtb
DTC [C] arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dtb
DTC [C] arch/riscv/boot/dts/tenstorrent/blackhole-a0-card.dtb
-------------------------------------------------
Thanks,
Drew
On 16/09/2025 18:27, Drew Fustini wrote:
> On Tue, Sep 16, 2025 at 02:56:05PM +0100, Ben Dooks wrote:
>> On 15/09/2025 18:52, Drew Fustini wrote:
>>> On Mon, Sep 15, 2025 at 05:47:08PM +0100, Conor Dooley wrote:
>>>> On Sat, Sep 13, 2025 at 02:31:05PM -0700, Drew Fustini wrote:
>>>>> new file mode 100644
>>>>> index 0000000000000000000000000000000000000000..b2b08023643a2cebd4f924579024290bb355c9b3
>>>>> --- /dev/null
>>>>> +++ b/arch/riscv/boot/dts/tenstorrent/blackhole-a0-card.dts
>>>>> @@ -0,0 +1,14 @@
>>>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>>>> +/dts-v1/;
>>>>> +
>>>>> +#include "blackhole-a0.dtsi"
>>>>> +
>>>>> +/ {
>>>>> + model = "Tenstorrent Blackhole A0 SoC PCIe card";
>>>>> + compatible = "tenstorrent,blackhole-a0-card", "tenstorrent,blackhole-a0";
>>>>> +
>>>>> + memory@0 {
>>>>> + device_type = "memory";
>>>>> + reg = <0x4000 0x30000000 0x1 0x00000000>;
>>>>
>>>> This isn't at address zero as the node address claims.
>>>
>>> Thanks, I'll fix the unit address.
>>
>> Is it time to just assume any dtc can handle a 64bit number?
>
> Is it not valid for me to use the 64 bit hex number in the unit address?
>
>
No, the reg = < > contents. It is a right pain to read split 32bit
numbers and I thought dtc had been updated to allow 64bit now?
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
https://www.codethink.co.uk/privacy.html
© 2016 - 2025 Red Hat, Inc.