From: Ciprian Costea <ciprianmarian.costea@nxp.com>

Define the list of Clock mode supported by PCIe

Signed-off-by: Ciprian Costea <ciprianmarian.costea@nxp.com>
Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
---
 include/linux/pcie/nxp-s32g-pcie-phy-submode.h | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 include/linux/pcie/nxp-s32g-pcie-phy-submode.h

diff --git a/include/linux/pcie/nxp-s32g-pcie-phy-submode.h b/include/linux/pcie/nxp-s32g-pcie-phy-submode.h
new file mode 100644
index 000000000000..2b96b5fd68c0
--- /dev/null
+++ b/include/linux/pcie/nxp-s32g-pcie-phy-submode.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/**
+ * Copyright 2021, 2025 NXP
+ */
+#ifndef NXP_S32G_PCIE_PHY_SUBMODE_H
+#define NXP_S32G_PCIE_PHY_SUBMODE_H
+
+enum pcie_phy_mode {
+	CRNS = 0, /* Common Reference Clock, No Spread Spectrum */
+	CRSS = 1, /* Common Reference Clock, Spread Spectrum */
+	SRNS = 2, /* Separate Reference Clock, No Spread Spectrum */
+	SRIS = 3  /* Separate Reference Clock, Independent Spread Spectrum */
+};
+
+#endif
-- 
2.43.0

On Fri, Sep 12, 2025 at 04:14:34PM +0200, Vincent Guittot wrote:
> From: Ciprian Costea <ciprianmarian.costea@nxp.com>
> 
> Define the list of Clock mode supported by PCIe
> 
> Signed-off-by: Ciprian Costea <ciprianmarian.costea@nxp.com>
> Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
> ---
>  include/linux/pcie/nxp-s32g-pcie-phy-submode.h | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>  create mode 100644 include/linux/pcie/nxp-s32g-pcie-phy-submode.h
> 
> diff --git a/include/linux/pcie/nxp-s32g-pcie-phy-submode.h b/include/linux/pcie/nxp-s32g-pcie-phy-submode.h
> new file mode 100644
> index 000000000000..2b96b5fd68c0
> --- /dev/null
> +++ b/include/linux/pcie/nxp-s32g-pcie-phy-submode.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/**
> + * Copyright 2021, 2025 NXP
> + */
> +#ifndef NXP_S32G_PCIE_PHY_SUBMODE_H
> +#define NXP_S32G_PCIE_PHY_SUBMODE_H
> +
> +enum pcie_phy_mode {
> +	CRNS = 0, /* Common Reference Clock, No Spread Spectrum */
> +	CRSS = 1, /* Common Reference Clock, Spread Spectrum */
> +	SRNS = 2, /* Separate Reference Clock, No Spread Spectrum */
> +	SRIS = 3  /* Separate Reference Clock, Independent Spread Spectrum */
> +};
> +
> +#endif

I doubt this belongs in include/linux/.  It looks like it should be in
pci-s32g.c since that's the only use.

On Sat, 13 Sept 2025 at 00:18, Bjorn Helgaas <helgaas@kernel.org> wrote:
>
> On Fri, Sep 12, 2025 at 04:14:34PM +0200, Vincent Guittot wrote:
> > From: Ciprian Costea <ciprianmarian.costea@nxp.com>
> >
> > Define the list of Clock mode supported by PCIe
> >
> > Signed-off-by: Ciprian Costea <ciprianmarian.costea@nxp.com>
> > Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
> > ---
> >  include/linux/pcie/nxp-s32g-pcie-phy-submode.h | 15 +++++++++++++++
> >  1 file changed, 15 insertions(+)
> >  create mode 100644 include/linux/pcie/nxp-s32g-pcie-phy-submode.h
> >
> > diff --git a/include/linux/pcie/nxp-s32g-pcie-phy-submode.h b/include/linux/pcie/nxp-s32g-pcie-phy-submode.h
> > new file mode 100644
> > index 000000000000..2b96b5fd68c0
> > --- /dev/null
> > +++ b/include/linux/pcie/nxp-s32g-pcie-phy-submode.h
> > @@ -0,0 +1,15 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/**
> > + * Copyright 2021, 2025 NXP
> > + */
> > +#ifndef NXP_S32G_PCIE_PHY_SUBMODE_H
> > +#define NXP_S32G_PCIE_PHY_SUBMODE_H
> > +
> > +enum pcie_phy_mode {
> > +     CRNS = 0, /* Common Reference Clock, No Spread Spectrum */
> > +     CRSS = 1, /* Common Reference Clock, Spread Spectrum */
> > +     SRNS = 2, /* Separate Reference Clock, No Spread Spectrum */
> > +     SRIS = 3  /* Separate Reference Clock, Independent Spread Spectrum */
> > +};
> > +
> > +#endif
>
> I doubt this belongs in include/linux/.  It looks like it should be in
> pci-s32g.c since that's the only use.

The header will be used by other driver so I didn't want to manage the
transition and a patchset which would includes drivers from different
areas