From: Irving-ch Lin <irving-ch.lin@mediatek.com>
Add device tree bindings for the power domains of MediaTek MT8189 SoC.
These definitions will be used to describe the power domain topology in
device tree sources.
Signed-off-by: Irving-ch Lin <irving-ch.lin@mediatek.com>
---
.../mediatek,mt8189-power-controller.yaml | 88 +++++++++++++++++++
.../dt-bindings/power/mediatek,mt8189-power.h | 38 ++++++++
2 files changed, 126 insertions(+)
create mode 100644 Documentation/devicetree/bindings/power/mediatek,mt8189-power-controller.yaml
create mode 100644 include/dt-bindings/power/mediatek,mt8189-power.h
diff --git a/Documentation/devicetree/bindings/power/mediatek,mt8189-power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,mt8189-power-controller.yaml
new file mode 100644
index 000000000000..71156f7edafe
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/mediatek,mt8189-power-controller.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/mediatek,mt8189-power-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Power Domains Controller for MT8189
+
+maintainers:
+ - Qiqi Wang <qiqi.wang@mediatek.com>
+
+description: |
+ MediaTek processors include support for multiple power domains which can be
+ powered up/down by software based on different application scenes to save power.
+
+ IP cores belonging to a power domain should contain a 'power-domains'
+ property that is a phandle for SCPSYS node representing the domain.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8189-scpsys
+
+ reg:
+ maxItems: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ clocks:
+ description: |
+ A number of phandles to clocks that need to be enabled during domain
+ power-up sequencing.
+
+ clock-names:
+ description: |
+ List of names of clocks, in order to match the power-up sequencing
+ for each power domain we need to group the clocks by name. BASIC
+ clocks need to be enabled before enabling the corresponding power
+ domain, and should not have a '-' in their name (i.e mm, mfg, venc).
+ SUSBYS clocks need to be enabled before releasing the bus protection,
+ and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
+
+ In order to follow properly the power-up sequencing, the clocks must
+ be specified by order, adding first the BASIC clocks followed by the
+ SUSBSYS clocks.
+
+patternProperties:
+ "^mfg[01]-supply$":
+ description: |
+ Regulator supply for mfg domain. With this attribute, scpsys can manage
+ mfg regulator in mtcmos control flow, to achieve low power scenario.
+
+required:
+ - compatible
+ - reg
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mediatek,mt8189-clk.h>
+ #include <dt-bindings/power/mediatek,mt8189-power.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ scpsys: power-controller@1c001000 {
+ compatible = "mediatek,mt8189-scpsys";
+ reg = <0 0x1c001000 0 0x1000>;
+ #power-domain-cells = <1>;
+ clocks = /* MFG */
+ <&topckgen_clk CLK_TOP_MFG_REF_SEL>,
+ <&apmixedsys_clk CLK_APMIXED_MFGPLL>;
+ clock-names = "mfg", "mfg_top";
+ mfg0-supply = <&mt6359_vproc1_buck_reg>;
+ mfg1-supply = <&mt6359_vsram_proc1_ldo_reg>;
+ };
+
+ /* Example of module to register power domain */
+ gpu: gpu@13000000 {
+ reg = <0 0x13000000 0 0x4000>;
+ power-domains = <&scpsys MT8189_POWER_DOMAIN_MFG2>,
+ <&scpsys MT8189_POWER_DOMAIN_MFG3>;
+ power-domain-names = "core0", "core1";
+ };
+ };
diff --git a/include/dt-bindings/power/mediatek,mt8189-power.h b/include/dt-bindings/power/mediatek,mt8189-power.h
new file mode 100644
index 000000000000..70a8c2113457
--- /dev/null
+++ b/include/dt-bindings/power/mediatek,mt8189-power.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Qiqi Wang <qiqi.wang@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT8189_POWER_H
+#define _DT_BINDINGS_POWER_MT8189_POWER_H
+
+/* SPM */
+#define MT8189_POWER_DOMAIN_CONN 0
+#define MT8189_POWER_DOMAIN_AUDIO 1
+#define MT8189_POWER_DOMAIN_ADSP_TOP_DORMANT 2
+#define MT8189_POWER_DOMAIN_ADSP_INFRA 3
+#define MT8189_POWER_DOMAIN_ADSP_AO 4
+#define MT8189_POWER_DOMAIN_MM_INFRA 5
+#define MT8189_POWER_DOMAIN_ISP_IMG1 6
+#define MT8189_POWER_DOMAIN_ISP_IMG2 7
+#define MT8189_POWER_DOMAIN_ISP_IPE 8
+#define MT8189_POWER_DOMAIN_VDE0 9
+#define MT8189_POWER_DOMAIN_VEN0 10
+#define MT8189_POWER_DOMAIN_CAM_MAIN 11
+#define MT8189_POWER_DOMAIN_CAM_SUBA 12
+#define MT8189_POWER_DOMAIN_CAM_SUBB 13
+#define MT8189_POWER_DOMAIN_MDP0 14
+#define MT8189_POWER_DOMAIN_DISP 15
+#define MT8189_POWER_DOMAIN_DP_TX 16
+#define MT8189_POWER_DOMAIN_CSI_RX 17
+#define MT8189_POWER_DOMAIN_SSUSB 18
+#define MT8189_POWER_DOMAIN_MFG0 19
+#define MT8189_POWER_DOMAIN_MFG1 20
+#define MT8189_POWER_DOMAIN_MFG2 21
+#define MT8189_POWER_DOMAIN_MFG3 22
+#define MT8189_POWER_DOMAIN_EDP_TX_DORMANT 23
+#define MT8189_POWER_DOMAIN_PCIE 24
+#define MT8189_POWER_DOMAIN_PCIE_PHY 25
+
+#endif /* _DT_BINDINGS_POWER_MT8189_POWER_H */
--
2.45.2On 12/09/2025 14:04, irving.ch.lin wrote:
> From: Irving-ch Lin <irving-ch.lin@mediatek.com>
>
> Add device tree bindings for the power domains of MediaTek MT8189 SoC.
> These definitions will be used to describe the power domain topology in
> device tree sources.
>
> Signed-off-by: Irving-ch Lin <irving-ch.lin@mediatek.com>
> ---
> .../mediatek,mt8189-power-controller.yaml | 88 +++++++++++++++++++
> .../dt-bindings/power/mediatek,mt8189-power.h | 38 ++++++++
> 2 files changed, 126 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/power/mediatek,mt8189-power-controller.yaml
> create mode 100644 include/dt-bindings/power/mediatek,mt8189-power.h
>
> diff --git a/Documentation/devicetree/bindings/power/mediatek,mt8189-power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,mt8189-power-controller.yaml
> new file mode 100644
> index 000000000000..71156f7edafe
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/power/mediatek,mt8189-power-controller.yaml
> @@ -0,0 +1,88 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/power/mediatek,mt8189-power-controller.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek Power Domains Controller for MT8189
> +
> +maintainers:
> + - Qiqi Wang <qiqi.wang@mediatek.com>
> +
> +description: |
> + MediaTek processors include support for multiple power domains which can be
> + powered up/down by software based on different application scenes to save power.
> +
> + IP cores belonging to a power domain should contain a 'power-domains'
> + property that is a phandle for SCPSYS node representing the domain.
> +
> +properties:
> + compatible:
> + enum:
> + - mediatek,mt8189-scpsys
> +
> + reg:
> + maxItems: 1
> +
> + '#power-domain-cells':
> + const: 1
> +
> + clocks:
> + description: |
> + A number of phandles to clocks that need to be enabled during domain
> + power-up sequencing.
Nothing improved, there is no such code in the bindings.
> +
> + clock-names:
> + description: |
> + List of names of clocks, in order to match the power-up sequencing
> + for each power domain we need to group the clocks by name. BASIC
Nothing improved here either.
> + clocks need to be enabled before enabling the corresponding power
> + domain, and should not have a '-' in their name (i.e mm, mfg, venc).
> + SUSBYS clocks need to be enabled before releasing the bus protection,
> + and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
> +
> + In order to follow properly the power-up sequencing, the clocks must
> + be specified by order, adding first the BASIC clocks followed by the
> + SUSBSYS clocks.
> +
> +patternProperties:
> + "^mfg[01]-supply$":
> + description: |
> + Regulator supply for mfg domain. With this attribute, scpsys can manage
> + mfg regulator in mtcmos control flow, to achieve low power scenario.
> +
> +required:
> + - compatible
> + - reg
> + - '#power-domain-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mediatek,mt8189-clk.h>
> + #include <dt-bindings/power/mediatek,mt8189-power.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + scpsys: power-controller@1c001000 {
> + compatible = "mediatek,mt8189-scpsys";
> + reg = <0 0x1c001000 0 0x1000>;
> + #power-domain-cells = <1>;
> + clocks = /* MFG */
> + <&topckgen_clk CLK_TOP_MFG_REF_SEL>,
> + <&apmixedsys_clk CLK_APMIXED_MFGPLL>;
> + clock-names = "mfg", "mfg_top";
> + mfg0-supply = <&mt6359_vproc1_buck_reg>;
> + mfg1-supply = <&mt6359_vsram_proc1_ldo_reg>;
> + };
> +
> + /* Example of module to register power domain */
What do the guidelines speak about this? Don't do this, don't add the
consumers. Drop.
The binding did not improve, so I am not doing full review. Please go
through writing bindings or tutorials/presentations explaining this, so
we won't need to repeat same comments.
Best regards,
Krzysztof
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