The pin-controller is used to control the Soc pins.
There are two pin-controllers on Cix Sky1 platform.
One is used under S0 state, the other is used under
S5 state.
Signed-off-by: Gary Yang <gary.yang@cixtech.com>
---
.../bindings/pinctrl/cix,sky1-pinctrl.yaml | 85 +++++++++++++++++++
1 file changed, 85 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml
new file mode 100644
index 000000000000..c4a127fd8330
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/cix,sky1-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cix Sky1 Pin Controller
+
+maintainers:
+ - Gary Yang <gary.yang@cixtech.com>
+
+description:
+ The pin-controller is used to control Soc pins. There are two pin-controllers
+ on Cix Sky1 platform. one is used under S0 state, the other one is used under
+ S5 state.
+
+properties:
+ compatible:
+ enum:
+ - cix,sky1-iomuxc
+ - cix,sky1-iomuxc-s5
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+# Client device subnode's properties
+patternProperties:
+ 'pins$':
+ type: object
+ additionalProperties: false
+ patternProperties:
+ '(^pins|pins?$)':
+ type: object
+ additionalProperties: false
+ description:
+ A pinctrl node should contain at least one subnodes representing the
+ pinctrl groups available on the machine. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to muxer
+ configuration, pullups, and drive strength.
+ $ref: /schemas/pinctrl/pincfg-node.yaml
+
+ properties:
+ pinmux:
+ description:
+ Integer array, represents gpio pin number and mux setting.
+ Supported pin number and mux varies for different SoCs, and are
+ defined as macros in arch/arm64/boot/dts/cix/sky1-pinfunc.h directly.
+
+ bias-disable: true
+
+ bias-pull-up: true
+
+ bias-pull-down: true
+
+ drive-strength:
+ description:
+ Can support 15 levels, from DS_LEVEL1 to DS_LEVEL15.
+ See arch/arm64/boot/dts/cix/sky1-pinfunc.h for valid arguments.
+
+ required:
+ - pinmux
+
+additionalProperties: false
+
+examples:
+ # Pinmux controller node
+ - |
+ #define CIX_PAD_GPIO012_FUNC_GPIO012 (11 << 8 | 0x0)
+ #define DS_LEVEL4 (4)
+ iomuxc: pinctrl@4170000 {
+ compatible = "cix,sky1-iomuxc";
+ reg = <0x4170000 0x1000>;
+
+ wifi_vbat_gpio: wifi-vbat-gpio-pins {
+ pins-wifi-vbat-gpio {
+ pinmux = <CIX_PAD_GPIO012_FUNC_GPIO012>;
+ bias-pull-up;
+ drive-strength = <DS_LEVEL4>;
+ };
+ };
+ };
--
2.49.0
On Fri, 12 Sep 2025 14:06:49 +0800, Gary Yang wrote:
> The pin-controller is used to control the Soc pins.
> There are two pin-controllers on Cix Sky1 platform.
> One is used under S0 state, the other is used under
> S5 state.
>
> Signed-off-by: Gary Yang <gary.yang@cixtech.com>
> ---
> .../bindings/pinctrl/cix,sky1-pinctrl.yaml | 85 +++++++++++++++++++
> 1 file changed, 85 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.example.dtb: wifi-vbat-gpio-pins: pins-wifi-vbat-gpio: {'pinmux': [2816], 'bias-pull-up': True, 'drive-strength': 4} is not of type 'array'
from schema $id: http://devicetree.org/schemas/gpio/gpio-consumer.yaml#
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250912060650.2180691-3-gary.yang@cixtech.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
On Fri, Sep 12, 2025 at 02:06:49PM +0800, Gary Yang wrote:
> The pin-controller is used to control the Soc pins.
> There are two pin-controllers on Cix Sky1 platform.
> One is used under S0 state, the other is used under
> S5 state.
Wrap lines at 72 chars.
>
> Signed-off-by: Gary Yang <gary.yang@cixtech.com>
> ---
> .../bindings/pinctrl/cix,sky1-pinctrl.yaml | 85 +++++++++++++++++++
> 1 file changed, 85 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml
> new file mode 100644
> index 000000000000..c4a127fd8330
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml
> @@ -0,0 +1,85 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/cix,sky1-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Cix Sky1 Pin Controller
> +
> +maintainers:
> + - Gary Yang <gary.yang@cixtech.com>
> +
> +description:
> + The pin-controller is used to control Soc pins. There are two pin-controllers
> + on Cix Sky1 platform. one is used under S0 state, the other one is used under
> + S5 state.
> +
> +properties:
> + compatible:
> + enum:
> + - cix,sky1-iomuxc
> + - cix,sky1-iomuxc-s5
> +
> + reg:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> +
> +# Client device subnode's properties
> +patternProperties:
> + 'pins$':
> + type: object
> + additionalProperties: false
> + patternProperties:
> + '(^pins|pins?$)':
> + type: object
> + additionalProperties: false
> + description:
> + A pinctrl node should contain at least one subnodes representing the
> + pinctrl groups available on the machine. Each subnode will list the
> + pins it needs, and how they should be configured, with regard to muxer
> + configuration, pullups, and drive strength.
> + $ref: /schemas/pinctrl/pincfg-node.yaml
> +
> + properties:
> + pinmux:
> + description:
> + Integer array, represents gpio pin number and mux setting.
> + Supported pin number and mux varies for different SoCs, and are
> + defined as macros in arch/arm64/boot/dts/cix/sky1-pinfunc.h directly.
> +
> + bias-disable: true
> +
> + bias-pull-up: true
> +
> + bias-pull-down: true
> +
> + drive-strength:
> + description:
> + Can support 15 levels, from DS_LEVEL1 to DS_LEVEL15.
> + See arch/arm64/boot/dts/cix/sky1-pinfunc.h for valid arguments.
Constraints on the values?
> +
> + required:
> + - pinmux
> +
> +additionalProperties: false
> +
> +examples:
> + # Pinmux controller node
> + - |
> + #define CIX_PAD_GPIO012_FUNC_GPIO012 (11 << 8 | 0x0)
> + #define DS_LEVEL4 (4)
> + iomuxc: pinctrl@4170000 {
> + compatible = "cix,sky1-iomuxc";
> + reg = <0x4170000 0x1000>;
> +
> + wifi_vbat_gpio: wifi-vbat-gpio-pins {
> + pins-wifi-vbat-gpio {
> + pinmux = <CIX_PAD_GPIO012_FUNC_GPIO012>;
> + bias-pull-up;
> + drive-strength = <DS_LEVEL4>;
> + };
> + };
> + };
> --
> 2.49.0
>
Hi Gary,
thanks for your patch!
Overall this is starting to look good.
Please make the bindings patch 1/3 because we usually put the bindings
first.
Some comments below!
On Fri, Sep 12, 2025 at 8:06 AM Gary Yang <gary.yang@cixtech.com> wrote:
> The pin-controller is used to control the Soc pins.
> There are two pin-controllers on Cix Sky1 platform.
> One is used under S0 state, the other is used under
> S5 state.
>
> Signed-off-by: Gary Yang <gary.yang@cixtech.com>
(...)
> +# Client device subnode's properties
> +patternProperties:
> + 'pins$':
> + type: object
> + additionalProperties: false
> + patternProperties:
> + '(^pins|pins?$)':
> + type: object
> + additionalProperties: false
> + description:
> + A pinctrl node should contain at least one subnodes representing the
> + pinctrl groups available on the machine. Each subnode will list the
> + pins it needs, and how they should be configured, with regard to muxer
> + configuration, pullups, and drive strength.
I'm not sure the binding maintainers want this info here, if the same is inside
pincfg-node.yaml, I would just skip it.
> + $ref: /schemas/pinctrl/pincfg-node.yaml
> +
> + properties:
> + pinmux:
> + description:
> + Integer array, represents gpio pin number and mux setting.
> + Supported pin number and mux varies for different SoCs, and are
> + defined as macros in arch/arm64/boot/dts/cix/sky1-pinfunc.h directly.
No reference to arch/arm64 in the bindings please. Just
drop this.
The bindings are used by U-Boot and FreeBSD as well so these
developers will be confused by any Linux-specific references.
> +
> + bias-disable: true
> +
> + bias-pull-up: true
> +
> + bias-pull-down: true
> +
> + drive-strength:
> + description:
> + Can support 15 levels, from DS_LEVEL1 to DS_LEVEL15.
> + See arch/arm64/boot/dts/cix/sky1-pinfunc.h for valid arguments.
Same thing.
> +
> + required:
> + - pinmux
> +
> +additionalProperties: false
> +
> +examples:
> + # Pinmux controller node
> + - |
> + #define CIX_PAD_GPIO012_FUNC_GPIO012 (11 << 8 | 0x0)
> + #define DS_LEVEL4 (4)
> + iomuxc: pinctrl@4170000 {
> + compatible = "cix,sky1-iomuxc";
> + reg = <0x4170000 0x1000>;
> +
> + wifi_vbat_gpio: wifi-vbat-gpio-pins {
> + pins-wifi-vbat-gpio {
> + pinmux = <CIX_PAD_GPIO012_FUNC_GPIO012>;
> + bias-pull-up;
> + drive-strength = <DS_LEVEL4>;
> + };
> + };
> + };
This looks good to me, I don't know if the bindings maintainers have
opinions on the placement of defines in examples.
Yours,
Linus Walleij
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