If the cached contents of the CHCONF register doesn't have the FORCE bit
set, the setup() function failed to set the relevant idle state of the
SPI_CLK pin. In such case, the SPI_CLK's idle state is reached later with
set_cs(), but it's too late for the first SPI transfer which fails since
the CS is asserted before the clock reaching its idle state.

Add a first write in setup() that always sets the FORCE bit.
Keep the current write afterwards to ensure the FORCE bit won't stay in
the cached contents of the CHCONF register unless it's intended.

Signed-off-by: Bastien Curutchet (Schneider Electric) <bastien.curutchet@bootlin.com>
---
Hi all,

I ran into this issue with a mode 3 SPI device. When the omap2-mcspi
driver probes, it sets mode 0 so the CLK is down. Then when the mode 3
SPI device probes, it asks for mode 3 but the clock doesn't go up.
Afterwards, when the first transfer occurs, the CS is asserted
before the clock actually reaches it's high state. This is interpreted
as a clock rising edge by the SPI device that samples one 'fake' bit
making this first transfer fail.
---
 drivers/spi/spi-omap2-mcspi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
index 6dc58a30804a12d16295a7ffc2edb192e6cc4a54..69c2e9d9be3c380327e26f94e82e05e6357f5384 100644
--- a/drivers/spi/spi-omap2-mcspi.c
+++ b/drivers/spi/spi-omap2-mcspi.c
@@ -988,6 +988,7 @@ static int omap2_mcspi_setup_transfer(struct spi_device *spi,
 	else
 		l &= ~OMAP2_MCSPI_CHCONF_PHA;
 
+	mcspi_write_chconf0(spi, l | OMAP2_MCSPI_CHCONF_FORCE);
 	mcspi_write_chconf0(spi, l);
 
 	cs->mode = spi->mode;

---
base-commit: 31623e6ce46bcdce751c0d242fbb1502746d1a7c
change-id: 20250911-omap-spi-fix-abfc560444a6

Best regards,
-- 
Bastien Curutchet (Schneider Electric) <bastien.curutchet@bootlin.com>

On Fri, 12 Sep 2025 09:08:58 +0200, Bastien Curutchet (Schneider Electric) wrote:
> If the cached contents of the CHCONF register doesn't have the FORCE bit
> set, the setup() function failed to set the relevant idle state of the
> SPI_CLK pin. In such case, the SPI_CLK's idle state is reached later with
> set_cs(), but it's too late for the first SPI transfer which fails since
> the CS is asserted before the clock reaching its idle state.
> 
> Add a first write in setup() that always sets the FORCE bit.
> Keep the current write afterwards to ensure the FORCE bit won't stay in
> the cached contents of the CHCONF register unless it's intended.
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[1/1] spi: omap2-mcspi: drive SPI_CLK on transfer_setup()
      commit: 398a8a4e51dbd03e4103ea596ea4ea037fe67175

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark