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[PATCH 3/3] riscv: dts: thead: add zfh for th1520

Han Gao posted 3 patches 5 months ago
There is a newer version of this series
[PATCH 3/3] riscv: dts: thead: add zfh for th1520
Posted by Han Gao 5 months ago 
th1520 support Zfh ISA extension [1].

Link: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1737721869472/%E7%8E%84%E9%93%81C910%E4%B8%8EC920R1S6%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C%28xrvm%29_20250124.pdf [1]

Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
 arch/riscv/boot/dts/thead/th1520.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 7f07688aa964..2075bb969c2f 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -26,7 +26,7 @@ c910_0: cpu@0 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <0>;
@@ -53,7 +53,7 @@ c910_1: cpu@1 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <1>;
@@ -80,7 +80,7 @@ c910_2: cpu@2 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <2>;
@@ -107,7 +107,7 @@ c910_3: cpu@3 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <3>;
-- 
2.47.3
Re: [PATCH 3/3] riscv: dts: thead: add zfh for th1520
Posted by Guo Ren 4 months, 4 weeks ago 
On Fri, Sep 12, 2025 at 2:46 AM Han Gao <rabenda.cn@gmail.com> wrote:
>
> th1520 support Zfh ISA extension [1].
>
> Link: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1737721869472/%E7%8E%84%E9%93%81C910%E4%B8%8EC920R1S6%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C%28xrvm%29_20250124.pdf [1]
Agree with Conor's advice.

Linus just had some comment about the Link tag usage:
https://www.phoronix.com/news/Linus-Torvalds-No-Link-Tags

We should be careful :-P

>
> Signed-off-by: Han Gao <rabenda.cn@gmail.com>
> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
> ---
>  arch/riscv/boot/dts/thead/th1520.dtsi | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> index 7f07688aa964..2075bb969c2f 100644
> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> @@ -26,7 +26,7 @@ c910_0: cpu@0 {
>                         riscv,isa-base = "rv64i";
>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>                                                "ziccrse", "zicntr", "zicsr",
> -                                              "zifencei", "zihpm",
> +                                              "zifencei", "zihpm", "zfh",
>                                                "xtheadvector";
>                         thead,vlenb = <16>;
>                         reg = <0>;
> @@ -53,7 +53,7 @@ c910_1: cpu@1 {
>                         riscv,isa-base = "rv64i";
>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>                                                "ziccrse", "zicntr", "zicsr",
> -                                              "zifencei", "zihpm",
> +                                              "zifencei", "zihpm", "zfh",
>                                                "xtheadvector";
>                         thead,vlenb = <16>;
>                         reg = <1>;
> @@ -80,7 +80,7 @@ c910_2: cpu@2 {
>                         riscv,isa-base = "rv64i";
>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>                                                "ziccrse", "zicntr", "zicsr",
> -                                              "zifencei", "zihpm",
> +                                              "zifencei", "zihpm", "zfh",
>                                                "xtheadvector";
>                         thead,vlenb = <16>;
>                         reg = <2>;
> @@ -107,7 +107,7 @@ c910_3: cpu@3 {
>                         riscv,isa-base = "rv64i";
>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>                                                "ziccrse", "zicntr", "zicsr",
> -                                              "zifencei", "zihpm",
> +                                              "zifencei", "zihpm", "zfh",
>                                                "xtheadvector";
>                         thead,vlenb = <16>;
>                         reg = <3>;
> --
> 2.47.3
>


-- 
Best Regards
 Guo Ren
Re: [PATCH 3/3] riscv: dts: thead: add zfh for th1520
Posted by Conor Dooley 4 months, 4 weeks ago 
On Fri, Sep 12, 2025 at 02:45:28AM +0800, Han Gao wrote:
> th1520 support Zfh ISA extension [1].
> 
> Link: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1737721869472/%E7%8E%84%E9%93%81C910%E4%B8%8EC920R1S6%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C%28xrvm%29_20250124.pdf [1]

Could you please cite the section that this is detailed in?

> 
> Signed-off-by: Han Gao <rabenda.cn@gmail.com>
> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
> ---
>  arch/riscv/boot/dts/thead/th1520.dtsi | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> index 7f07688aa964..2075bb969c2f 100644
> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> @@ -26,7 +26,7 @@ c910_0: cpu@0 {
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>  					       "ziccrse", "zicntr", "zicsr",
> -					       "zifencei", "zihpm",
> +					       "zifencei", "zihpm", "zfh",
>  					       "xtheadvector";
>  			thead,vlenb = <16>;
>  			reg = <0>;
> @@ -53,7 +53,7 @@ c910_1: cpu@1 {
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>  					       "ziccrse", "zicntr", "zicsr",
> -					       "zifencei", "zihpm",
> +					       "zifencei", "zihpm", "zfh",
>  					       "xtheadvector";
>  			thead,vlenb = <16>;
>  			reg = <1>;
> @@ -80,7 +80,7 @@ c910_2: cpu@2 {
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>  					       "ziccrse", "zicntr", "zicsr",
> -					       "zifencei", "zihpm",
> +					       "zifencei", "zihpm", "zfh",
>  					       "xtheadvector";
>  			thead,vlenb = <16>;
>  			reg = <2>;
> @@ -107,7 +107,7 @@ c910_3: cpu@3 {
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>  					       "ziccrse", "zicntr", "zicsr",
> -					       "zifencei", "zihpm",
> +					       "zifencei", "zihpm", "zfh",
>  					       "xtheadvector";
>  			thead,vlenb = <16>;
>  			reg = <3>;
> -- 
> 2.47.3
> 
> 
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