Convert the existing text-based DT bindings for MediaTek MT8173 Media Data
Path to a DT schema.
Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
---
.../bindings/media/mediatek,mt8173-mdp.yaml | 169 ++++++++++++++++++
.../bindings/media/mediatek-mdp.txt | 95 ----------
2 files changed, 169 insertions(+), 95 deletions(-)
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml
delete mode 100644 Documentation/devicetree/bindings/media/mediatek-mdp.txt
diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml
new file mode 100644
index 0000000000000..8ca33a733c478
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml
@@ -0,0 +1,169 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mt8173-mdp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MT8173 Media Data Path
+
+maintainers:
+ - Ariel D'Alessandro <ariel.dalessandro@collabora.com>
+
+description:
+ Media Data Path is used for scaling and color space conversion.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - mediatek,mt8173-mdp-rdma
+ - mediatek,mt8173-mdp-rsz
+ - mediatek,mt8173-mdp-wdma
+ - mediatek,mt8173-mdp-wrot
+ - items:
+ - const: mediatek,mt8173-mdp-rdma
+ - const: mediatek,mt8173-mdp
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ power-domains:
+ maxItems: 1
+
+ iommus:
+ maxItems: 1
+
+ mediatek,vpu:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ phandle to Mediatek Video Processor Unit for HW Codec encode/decode and
+ image processing.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - power-domains
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8173-mdp-rdma
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Main clock
+ - description: Mutex clock
+ else:
+ properties:
+ clocks:
+ items:
+ - description: Main clock
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mediatek,mt8173-mdp-rdma
+ - mediatek,mt8173-mdp-wdma
+ - mediatek,mt8173-mdp-wrot
+ then:
+ required:
+ - iommus
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8173-mdp
+ then:
+ required:
+ - mediatek,vpu
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/memory/mt8173-larb-port.h>
+ #include <dt-bindings/power/mt8173-power.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ mdp_rdma0: rdma@14001000 {
+ compatible = "mediatek,mt8173-mdp-rdma",
+ "mediatek,mt8173-mdp";
+ reg = <0 0x14001000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RDMA0>,
+ <&mmsys CLK_MM_MUTEX_32K>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+ iommus = <&iommu M4U_PORT_MDP_RDMA0>;
+ mediatek,vpu = <&vpu>;
+ };
+
+ mdp_rdma1: rdma@14002000 {
+ compatible = "mediatek,mt8173-mdp-rdma";
+ reg = <0 0x14002000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RDMA1>,
+ <&mmsys CLK_MM_MUTEX_32K>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+ iommus = <&iommu M4U_PORT_MDP_RDMA1>;
+ };
+
+ mdp_rsz0: rsz@14003000 {
+ compatible = "mediatek,mt8173-mdp-rsz";
+ reg = <0 0x14003000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ0>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+ };
+
+ mdp_rsz1: rsz@14004000 {
+ compatible = "mediatek,mt8173-mdp-rsz";
+ reg = <0 0x14004000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ1>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+ };
+
+ mdp_rsz2: rsz@14005000 {
+ compatible = "mediatek,mt8173-mdp-rsz";
+ reg = <0 0x14005000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ2>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+ };
+
+ mdp_wdma0: wdma@14006000 {
+ compatible = "mediatek,mt8173-mdp-wdma";
+ reg = <0 0x14006000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_WDMA>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+ iommus = <&iommu M4U_PORT_MDP_WDMA>;
+ };
+
+ mdp_wrot0: wrot@14007000 {
+ compatible = "mediatek,mt8173-mdp-wrot";
+ reg = <0 0x14007000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_WROT0>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+ iommus = <&iommu M4U_PORT_MDP_WROT0>;
+ };
+
+ mdp_wrot1: wrot@14008000 {
+ compatible = "mediatek,mt8173-mdp-wrot";
+ reg = <0 0x14008000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_WROT1>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+ iommus = <&iommu M4U_PORT_MDP_WROT1>;
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/media/mediatek-mdp.txt b/Documentation/devicetree/bindings/media/mediatek-mdp.txt
deleted file mode 100644
index 53ef26e2c8570..0000000000000
--- a/Documentation/devicetree/bindings/media/mediatek-mdp.txt
+++ /dev/null
@@ -1,95 +0,0 @@
-* Mediatek Media Data Path
-
-Media Data Path is used for scaling and color space conversion.
-
-Required properties (controller node):
-- compatible: "mediatek,mt8173-mdp"
-- mediatek,vpu: the node of video processor unit, see
- Documentation/devicetree/bindings/media/mediatek-vpu.txt for details.
-
-Required properties (all function blocks, child node):
-- compatible: Should be one of
- "mediatek,mt8173-mdp-rdma" - read DMA
- "mediatek,mt8173-mdp-rsz" - resizer
- "mediatek,mt8173-mdp-wdma" - write DMA
- "mediatek,mt8173-mdp-wrot" - write DMA with rotation
-- reg: Physical base address and length of the function block register space
-- clocks: device clocks, see
- Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
-- power-domains: a phandle to the power domain, see
- Documentation/devicetree/bindings/power/power_domain.txt for details.
-
-Required properties (DMA function blocks, child node):
-- compatible: Should be one of
- "mediatek,mt8173-mdp-rdma"
- "mediatek,mt8173-mdp-wdma"
- "mediatek,mt8173-mdp-wrot"
-- iommus: should point to the respective IOMMU block with master port as
- argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
- for details.
-
-Example:
- mdp_rdma0: rdma@14001000 {
- compatible = "mediatek,mt8173-mdp-rdma";
- "mediatek,mt8173-mdp";
- reg = <0 0x14001000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_RDMA0>,
- <&mmsys CLK_MM_MUTEX_32K>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- iommus = <&iommu M4U_PORT_MDP_RDMA0>;
- mediatek,vpu = <&vpu>;
- };
-
- mdp_rdma1: rdma@14002000 {
- compatible = "mediatek,mt8173-mdp-rdma";
- reg = <0 0x14002000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_RDMA1>,
- <&mmsys CLK_MM_MUTEX_32K>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- iommus = <&iommu M4U_PORT_MDP_RDMA1>;
- };
-
- mdp_rsz0: rsz@14003000 {
- compatible = "mediatek,mt8173-mdp-rsz";
- reg = <0 0x14003000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_RSZ0>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- };
-
- mdp_rsz1: rsz@14004000 {
- compatible = "mediatek,mt8173-mdp-rsz";
- reg = <0 0x14004000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_RSZ1>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- };
-
- mdp_rsz2: rsz@14005000 {
- compatible = "mediatek,mt8173-mdp-rsz";
- reg = <0 0x14005000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_RSZ2>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- };
-
- mdp_wdma0: wdma@14006000 {
- compatible = "mediatek,mt8173-mdp-wdma";
- reg = <0 0x14006000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_WDMA>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- iommus = <&iommu M4U_PORT_MDP_WDMA>;
- };
-
- mdp_wrot0: wrot@14007000 {
- compatible = "mediatek,mt8173-mdp-wrot";
- reg = <0 0x14007000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_WROT0>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- iommus = <&iommu M4U_PORT_MDP_WROT0>;
- };
-
- mdp_wrot1: wrot@14008000 {
- compatible = "mediatek,mt8173-mdp-wrot";
- reg = <0 0x14008000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_WROT1>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- iommus = <&iommu M4U_PORT_MDP_WROT1>;
- };
--
2.50.1Il 11/09/25 17:09, Ariel D'Alessandro ha scritto:
> Convert the existing text-based DT bindings for MediaTek MT8173 Media Data
> Path to a DT schema.
>
> Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> .../bindings/media/mediatek,mt8173-mdp.yaml | 169 ++++++++++++++++++
> .../bindings/media/mediatek-mdp.txt | 95 ----------
> 2 files changed, 169 insertions(+), 95 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml
> delete mode 100644 Documentation/devicetree/bindings/media/mediatek-mdp.txt
>
> diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml
> new file mode 100644
> index 0000000000000..8ca33a733c478
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml
> @@ -0,0 +1,169 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/mediatek,mt8173-mdp.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek MT8173 Media Data Path
> +
> +maintainers:
> + - Ariel D'Alessandro <ariel.dalessandro@collabora.com>
> +
> +description:
> + Media Data Path is used for scaling and color space conversion.
> +
> +properties:
> + compatible:
> + oneOf:
> + - enum:
> + - mediatek,mt8173-mdp-rdma
> + - mediatek,mt8173-mdp-rsz
> + - mediatek,mt8173-mdp-wdma
> + - mediatek,mt8173-mdp-wrot
> + - items:
> + - const: mediatek,mt8173-mdp-rdma
> + - const: mediatek,mt8173-mdp
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + minItems: 1
> + maxItems: 2
> +
> + power-domains:
> + maxItems: 1
> +
> + iommus:
> + maxItems: 1
> +
> + mediatek,vpu:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + phandle to Mediatek Video Processor Unit for HW Codec encode/decode and
> + image processing.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - power-domains
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: mediatek,mt8173-mdp-rdma
> + then:
> + properties:
> + clocks:
> + items:
> + - description: Main clock
> + - description: Mutex clock
> + else:
> + properties:
> + clocks:
> + items:
> + - description: Main clock
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - mediatek,mt8173-mdp-rdma
> + - mediatek,mt8173-mdp-wdma
> + - mediatek,mt8173-mdp-wrot
> + then:
> + required:
> + - iommus
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: mediatek,mt8173-mdp
> + then:
> + required:
> + - mediatek,vpu
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt8173-clk.h>
> + #include <dt-bindings/memory/mt8173-larb-port.h>
> + #include <dt-bindings/power/mt8173-power.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + mdp_rdma0: rdma@14001000 {
> + compatible = "mediatek,mt8173-mdp-rdma",
> + "mediatek,mt8173-mdp";
> + reg = <0 0x14001000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_RDMA0>,
> + <&mmsys CLK_MM_MUTEX_32K>;
> + power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> + iommus = <&iommu M4U_PORT_MDP_RDMA0>;
> + mediatek,vpu = <&vpu>;
> + };
> +
> + mdp_rdma1: rdma@14002000 {
> + compatible = "mediatek,mt8173-mdp-rdma";
> + reg = <0 0x14002000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_RDMA1>,
> + <&mmsys CLK_MM_MUTEX_32K>;
> + power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> + iommus = <&iommu M4U_PORT_MDP_RDMA1>;
> + };
> +
> + mdp_rsz0: rsz@14003000 {
> + compatible = "mediatek,mt8173-mdp-rsz";
> + reg = <0 0x14003000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_RSZ0>;
> + power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> + };
> +
> + mdp_rsz1: rsz@14004000 {
> + compatible = "mediatek,mt8173-mdp-rsz";
> + reg = <0 0x14004000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_RSZ1>;
> + power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> + };
> +
> + mdp_rsz2: rsz@14005000 {
> + compatible = "mediatek,mt8173-mdp-rsz";
> + reg = <0 0x14005000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_RSZ2>;
> + power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> + };
> +
> + mdp_wdma0: wdma@14006000 {
> + compatible = "mediatek,mt8173-mdp-wdma";
> + reg = <0 0x14006000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_WDMA>;
> + power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> + iommus = <&iommu M4U_PORT_MDP_WDMA>;
> + };
> +
> + mdp_wrot0: wrot@14007000 {
> + compatible = "mediatek,mt8173-mdp-wrot";
> + reg = <0 0x14007000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_WROT0>;
> + power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> + iommus = <&iommu M4U_PORT_MDP_WROT0>;
> + };
> +
> + mdp_wrot1: wrot@14008000 {
> + compatible = "mediatek,mt8173-mdp-wrot";
> + reg = <0 0x14008000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_WROT1>;
> + power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> + iommus = <&iommu M4U_PORT_MDP_WROT1>;
> + };
> + };
> +
> +...
On Thu, Sep 11, 2025 at 12:09:50PM -0300, Ariel D'Alessandro wrote:
> Convert the existing text-based DT bindings for MediaTek MT8173 Media Data
> Path to a DT schema.
>
> Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
> ---
> .../bindings/media/mediatek,mt8173-mdp.yaml | 169 ++++++++++++++++++
> .../bindings/media/mediatek-mdp.txt | 95 ----------
> 2 files changed, 169 insertions(+), 95 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml
> delete mode 100644 Documentation/devicetree/bindings/media/mediatek-mdp.txt
>
> diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml
> new file mode 100644
> index 0000000000000..8ca33a733c478
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml
> @@ -0,0 +1,169 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/mediatek,mt8173-mdp.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek MT8173 Media Data Path
> +
> +maintainers:
> + - Ariel D'Alessandro <ariel.dalessandro@collabora.com>
> +
> +description:
> + Media Data Path is used for scaling and color space conversion.
> +
> +properties:
> + compatible:
> + oneOf:
> + - enum:
> + - mediatek,mt8173-mdp-rdma
> + - mediatek,mt8173-mdp-rsz
> + - mediatek,mt8173-mdp-wdma
> + - mediatek,mt8173-mdp-wrot
Why there is no mediatek,mt8173-mdp here? What does this compatible
represent?
> + - items:
> + - const: mediatek,mt8173-mdp-rdma
Still suspicious. Device cannot be simulatanously: compatible and not
compatible. This is not a well known cat that has superposition of two
states, whenenver you look the other way.
Maybe the old binding was incorrect, maybe the in-tree DTS is incorrect.
Whichever the reason, this must be investigated and documented, because
by standard rules this is wrong. Each wrong code needs very clear
explanations (and "someone did it" is not a good enough explanation).
> + - const: mediatek,mt8173-mdp
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + minItems: 1
> + maxItems: 2
> +
> + power-domains:
> + maxItems: 1
> +
> + iommus:
> + maxItems: 1
> +
> + mediatek,vpu:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + phandle to Mediatek Video Processor Unit for HW Codec encode/decode and
> + image processing.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - power-domains
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: mediatek,mt8173-mdp-rdma
> + then:
> + properties:
> + clocks:
> + items:
> + - description: Main clock
> + - description: Mutex clock
> + else:
> + properties:
> + clocks:
> + items:
> + - description: Main clock
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - mediatek,mt8173-mdp-rdma
> + - mediatek,mt8173-mdp-wdma
> + - mediatek,mt8173-mdp-wrot
> + then:
> + required:
> + - iommus
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: mediatek,mt8173-mdp
> + then:
> + required:
> + - mediatek,vpu
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt8173-clk.h>
> + #include <dt-bindings/memory/mt8173-larb-port.h>
> + #include <dt-bindings/power/mt8173-power.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + mdp_rdma0: rdma@14001000 {
> + compatible = "mediatek,mt8173-mdp-rdma",
> + "mediatek,mt8173-mdp";
> + reg = <0 0x14001000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_RDMA0>,
> + <&mmsys CLK_MM_MUTEX_32K>;
> + power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> + iommus = <&iommu M4U_PORT_MDP_RDMA0>;
> + mediatek,vpu = <&vpu>;
> + };
> +
> + mdp_rdma1: rdma@14002000 {
> + compatible = "mediatek,mt8173-mdp-rdma";
> + reg = <0 0x14002000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_RDMA1>,
> + <&mmsys CLK_MM_MUTEX_32K>;
> + power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> + iommus = <&iommu M4U_PORT_MDP_RDMA1>;
> + };
My previous comment applies.
Keep one or two examples.
Best regards,
Krzysztof
On Fri, Sep 12, 2025 at 2:06 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On Thu, Sep 11, 2025 at 12:09:50PM -0300, Ariel D'Alessandro wrote:
> > Convert the existing text-based DT bindings for MediaTek MT8173 Media Data
> > Path to a DT schema.
> >
> > Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
> > ---
> > .../bindings/media/mediatek,mt8173-mdp.yaml | 169 ++++++++++++++++++
> > .../bindings/media/mediatek-mdp.txt | 95 ----------
> > 2 files changed, 169 insertions(+), 95 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml
> > delete mode 100644 Documentation/devicetree/bindings/media/mediatek-mdp.txt
> >
> > diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml
> > new file mode 100644
> > index 0000000000000..8ca33a733c478
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml
> > @@ -0,0 +1,169 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/media/mediatek,mt8173-mdp.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MediaTek MT8173 Media Data Path
> > +
> > +maintainers:
> > + - Ariel D'Alessandro <ariel.dalessandro@collabora.com>
> > +
> > +description:
> > + Media Data Path is used for scaling and color space conversion.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - enum:
> > + - mediatek,mt8173-mdp-rdma
> > + - mediatek,mt8173-mdp-rsz
> > + - mediatek,mt8173-mdp-wdma
> > + - mediatek,mt8173-mdp-wrot
>
> Why there is no mediatek,mt8173-mdp here? What does this compatible
> represent?
>
> > + - items:
> > + - const: mediatek,mt8173-mdp-rdma
>
> Still suspicious. Device cannot be simulatanously: compatible and not
> compatible. This is not a well known cat that has superposition of two
> states, whenenver you look the other way.
>
> Maybe the old binding was incorrect, maybe the in-tree DTS is incorrect.
> Whichever the reason, this must be investigated and documented, because
> by standard rules this is wrong. Each wrong code needs very clear
> explanations (and "someone did it" is not a good enough explanation).
My guess is that "mediatek,mt8173-mdp" is meant to serve as a single
entry point for the implementation to bind the driver to. The MDP is
a Data Pipeline and there could be multiple instances of the same
IP block, as seen in the original example.
The datasheet I have doesn't cover the "RDMA" block specifically, so
I can't say whether there is an actual difference between the two RDMA
blocks.
ChenYu
> > + - const: mediatek,mt8173-mdp
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + minItems: 1
> > + maxItems: 2
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + iommus:
> > + maxItems: 1
> > +
> > + mediatek,vpu:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description:
> > + phandle to Mediatek Video Processor Unit for HW Codec encode/decode and
> > + image processing.
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > + - power-domains
> > +
> > +allOf:
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: mediatek,mt8173-mdp-rdma
> > + then:
> > + properties:
> > + clocks:
> > + items:
> > + - description: Main clock
> > + - description: Mutex clock
> > + else:
> > + properties:
> > + clocks:
> > + items:
> > + - description: Main clock
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - mediatek,mt8173-mdp-rdma
> > + - mediatek,mt8173-mdp-wdma
> > + - mediatek,mt8173-mdp-wrot
> > + then:
> > + required:
> > + - iommus
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: mediatek,mt8173-mdp
> > + then:
> > + required:
> > + - mediatek,vpu
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/mt8173-clk.h>
> > + #include <dt-bindings/memory/mt8173-larb-port.h>
> > + #include <dt-bindings/power/mt8173-power.h>
> > +
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + mdp_rdma0: rdma@14001000 {
> > + compatible = "mediatek,mt8173-mdp-rdma",
> > + "mediatek,mt8173-mdp";
> > + reg = <0 0x14001000 0 0x1000>;
> > + clocks = <&mmsys CLK_MM_MDP_RDMA0>,
> > + <&mmsys CLK_MM_MUTEX_32K>;
> > + power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> > + iommus = <&iommu M4U_PORT_MDP_RDMA0>;
> > + mediatek,vpu = <&vpu>;
> > + };
> > +
> > + mdp_rdma1: rdma@14002000 {
> > + compatible = "mediatek,mt8173-mdp-rdma";
> > + reg = <0 0x14002000 0 0x1000>;
> > + clocks = <&mmsys CLK_MM_MDP_RDMA1>,
> > + <&mmsys CLK_MM_MUTEX_32K>;
> > + power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> > + iommus = <&iommu M4U_PORT_MDP_RDMA1>;
> > + };
>
> My previous comment applies.
>
> Keep one or two examples.
>
> Best regards,
> Krzysztof
>
On 12/09/2025 10:27, Chen-Yu Tsai wrote: >>> +properties: >>> + compatible: >>> + oneOf: >>> + - enum: >>> + - mediatek,mt8173-mdp-rdma >>> + - mediatek,mt8173-mdp-rsz >>> + - mediatek,mt8173-mdp-wdma >>> + - mediatek,mt8173-mdp-wrot >> >> Why there is no mediatek,mt8173-mdp here? What does this compatible >> represent? >> >>> + - items: >>> + - const: mediatek,mt8173-mdp-rdma >> >> Still suspicious. Device cannot be simulatanously: compatible and not >> compatible. This is not a well known cat that has superposition of two >> states, whenenver you look the other way. >> >> Maybe the old binding was incorrect, maybe the in-tree DTS is incorrect. >> Whichever the reason, this must be investigated and documented, because >> by standard rules this is wrong. Each wrong code needs very clear >> explanations (and "someone did it" is not a good enough explanation). > > My guess is that "mediatek,mt8173-mdp" is meant to serve as a single > entry point for the implementation to bind the driver to. The MDP is I am speaking about hardware. What piece of hardware it implements and why sometimes it is RDMA MDP and sometimes it is not RDMA MDP, but only MDP. > a Data Pipeline and there could be multiple instances of the same > IP block, as seen in the original example. > > The datasheet I have doesn't cover the "RDMA" block specifically, so > I can't say whether there is an actual difference between the two RDMA > blocks. > > Best regards, Krzysztof
Il 12/09/25 10:27, Chen-Yu Tsai ha scritto:
> On Fri, Sep 12, 2025 at 2:06 PM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>
>> On Thu, Sep 11, 2025 at 12:09:50PM -0300, Ariel D'Alessandro wrote:
>>> Convert the existing text-based DT bindings for MediaTek MT8173 Media Data
>>> Path to a DT schema.
>>>
>>> Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
>>> ---
>>> .../bindings/media/mediatek,mt8173-mdp.yaml | 169 ++++++++++++++++++
>>> .../bindings/media/mediatek-mdp.txt | 95 ----------
>>> 2 files changed, 169 insertions(+), 95 deletions(-)
>>> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml
>>> delete mode 100644 Documentation/devicetree/bindings/media/mediatek-mdp.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml
>>> new file mode 100644
>>> index 0000000000000..8ca33a733c478
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml
>>> @@ -0,0 +1,169 @@
>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/media/mediatek,mt8173-mdp.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: MediaTek MT8173 Media Data Path
>>> +
>>> +maintainers:
>>> + - Ariel D'Alessandro <ariel.dalessandro@collabora.com>
>>> +
>>> +description:
>>> + Media Data Path is used for scaling and color space conversion.
>>> +
>>> +properties:
>>> + compatible:
>>> + oneOf:
>>> + - enum:
>>> + - mediatek,mt8173-mdp-rdma
>>> + - mediatek,mt8173-mdp-rsz
>>> + - mediatek,mt8173-mdp-wdma
>>> + - mediatek,mt8173-mdp-wrot
>>
>> Why there is no mediatek,mt8173-mdp here? What does this compatible
>> represent?
>>
>>> + - items:
>>> + - const: mediatek,mt8173-mdp-rdma
>>
>> Still suspicious. Device cannot be simulatanously: compatible and not
>> compatible. This is not a well known cat that has superposition of two
>> states, whenenver you look the other way.
>>
>> Maybe the old binding was incorrect, maybe the in-tree DTS is incorrect.
>> Whichever the reason, this must be investigated and documented, because
>> by standard rules this is wrong. Each wrong code needs very clear
>> explanations (and "someone did it" is not a good enough explanation).
>
> My guess is that "mediatek,mt8173-mdp" is meant to serve as a single
> entry point for the implementation to bind the driver to. The MDP is
> a Data Pipeline and there could be multiple instances of the same
> IP block, as seen in the original example.
>
Yeah your guess is right.
Cheers,
Angelo
> The datasheet I have doesn't cover the "RDMA" block specifically, so
> I can't say whether there is an actual difference between the two RDMA
> blocks.
>
>
> ChenYu
>
>>> + - const: mediatek,mt8173-mdp
>>> +
>>> + reg:
>>> + maxItems: 1
>>> +
>>> + clocks:
>>> + minItems: 1
>>> + maxItems: 2
>>> +
>>> + power-domains:
>>> + maxItems: 1
>>> +
>>> + iommus:
>>> + maxItems: 1
>>> +
>>> + mediatek,vpu:
>>> + $ref: /schemas/types.yaml#/definitions/phandle
>>> + description:
>>> + phandle to Mediatek Video Processor Unit for HW Codec encode/decode and
>>> + image processing.
>>> +
>>> +required:
>>> + - compatible
>>> + - reg
>>> + - clocks
>>> + - power-domains
>>> +
>>> +allOf:
>>> + - if:
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + const: mediatek,mt8173-mdp-rdma
>>> + then:
>>> + properties:
>>> + clocks:
>>> + items:
>>> + - description: Main clock
>>> + - description: Mutex clock
>>> + else:
>>> + properties:
>>> + clocks:
>>> + items:
>>> + - description: Main clock
>>> +
>>> + - if:
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + enum:
>>> + - mediatek,mt8173-mdp-rdma
>>> + - mediatek,mt8173-mdp-wdma
>>> + - mediatek,mt8173-mdp-wrot
>>> + then:
>>> + required:
>>> + - iommus
>>> +
>>> + - if:
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + const: mediatek,mt8173-mdp
>>> + then:
>>> + required:
>>> + - mediatek,vpu
>>> +
>>> +additionalProperties: false
>>> +
>>> +examples:
>>> + - |
>>> + #include <dt-bindings/clock/mt8173-clk.h>
>>> + #include <dt-bindings/memory/mt8173-larb-port.h>
>>> + #include <dt-bindings/power/mt8173-power.h>
>>> +
>>> + soc {
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> +
>>> + mdp_rdma0: rdma@14001000 {
>>> + compatible = "mediatek,mt8173-mdp-rdma",
>>> + "mediatek,mt8173-mdp";
>>> + reg = <0 0x14001000 0 0x1000>;
>>> + clocks = <&mmsys CLK_MM_MDP_RDMA0>,
>>> + <&mmsys CLK_MM_MUTEX_32K>;
>>> + power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
>>> + iommus = <&iommu M4U_PORT_MDP_RDMA0>;
>>> + mediatek,vpu = <&vpu>;
>>> + };
>>> +
>>> + mdp_rdma1: rdma@14002000 {
>>> + compatible = "mediatek,mt8173-mdp-rdma";
>>> + reg = <0 0x14002000 0 0x1000>;
>>> + clocks = <&mmsys CLK_MM_MDP_RDMA1>,
>>> + <&mmsys CLK_MM_MUTEX_32K>;
>>> + power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
>>> + iommus = <&iommu M4U_PORT_MDP_RDMA1>;
>>> + };
>>
>> My previous comment applies.
>>
>> Keep one or two examples.
>>
>> Best regards,
>> Krzysztof
>>
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