From: Chen Pei <cp0613@linux.alibaba.com>
This patch has added property definitions related to the riscv
trace component, providing a foundation for subsequent driver
implementations.
The RISC-V Trace Control Interface can be found in [1].
Some principles are as follows:
1. Trace has three types of components:
1.1 Encoder: Collects CPU execution information through the
Ingress Port and generates Trace Messages.
1.2 Funnel: Used to integrate multiple trace sources.
1.3 Sink: Used to store trace data.
2. Each hart requires one trace encoder.
3. When there are multiple trace sources, a trace funnel component
is needed to integrate them. One trace funnel is required for
each cluster.
4. When multiple trace funnels are fed into a single trace sink,
multiple levels of trace funnels are required.
5. If there is only one cluster, the trace funnel (Level 0) can be
connected directly to the trace sink.
Taking [cpu0]-->[encoder0]-->[funnel0]-->[sink0] as an example,
the DTS configuration is as follows:
encoder0: trace_encoder@26001000 {
compatible = "riscv_trace,encoder-controller";
reg = <0x0 0x26001000 0x0 0x1000>;
cpu = <&cpu0>;
output_port {
port0 {
endpoint = <&funnel0>;
};
};
};
funnel0: trace_funnel@26404000 {
compatible = "riscv_trace,funnel-controller";
reg = <0x0 0x26404000 0x0 0x1000>;
level = <1>;
input_port {
port0 {
endpoint = <&encoder0>;
};
};
output_port {
port0 {
endpoint = <&sink0>;
};
};
};
sink0: trace_sink@26401000 {
compatible = "riscv_trace,sink-controller";
reg = <0x0 0x26401000 0x0 0x1000>;
input_port {
port0 {
endpoint = <&funnel0>;
};
};
};
Note: The detailed property definition of each component will be
provided in the subsequent series of patches.
[1] https://github.com/riscv-non-isa/tg-nexus-trace.git
Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
---
.../riscv/trace/riscv,trace,encoder.yaml | 41 +++++++++++++++++
.../riscv/trace/riscv,trace,funnel.yaml | 46 +++++++++++++++++++
.../riscv/trace/riscv,trace,sink.yaml | 37 +++++++++++++++
3 files changed, 124 insertions(+)
create mode 100644 Documentation/devicetree/bindings/riscv/trace/riscv,trace,encoder.yaml
create mode 100644 Documentation/devicetree/bindings/riscv/trace/riscv,trace,funnel.yaml
create mode 100644 Documentation/devicetree/bindings/riscv/trace/riscv,trace,sink.yaml
diff --git a/Documentation/devicetree/bindings/riscv/trace/riscv,trace,encoder.yaml b/Documentation/devicetree/bindings/riscv/trace/riscv,trace,encoder.yaml
new file mode 100644
index 000000000000..e2ec3ce514b2
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/trace/riscv,trace,encoder.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/trace/riscv,trace,encoder.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RISC-V Trace Encoder Controller
+
+description: |
+ riscv trace encoder controller description.
+
+maintainers:
+ - Chen Pei <cp0613@linux.alibaba.com>
+
+properties:
+ compatible:
+ items:
+ - const: riscv_trace,encoder-controller
+ reg:
+ description: A memory region containing registers for encoder controller
+
+ cpu:
+ description: CPU identifier associated with this encoder
+
+ ports:
+ description: Output port definitions
+
+additionalProperties: true
+
+examples:
+ - |
+ encoder0: trace_encoder@26001000 {
+ compatible = "riscv_trace,encoder-controller";
+ reg = <0x0 0x26001000 0x0 0x1000>;
+ cpu = <&cpu0>;
+ output_port {
+ port0 {
+ endpoint = <&funnel0>;
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/riscv/trace/riscv,trace,funnel.yaml b/Documentation/devicetree/bindings/riscv/trace/riscv,trace,funnel.yaml
new file mode 100644
index 000000000000..5da836997355
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/trace/riscv,trace,funnel.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/trace/riscv,trace,funnel.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RISC-V Trace Funnel Controller
+
+description: |
+ riscv trace funnel controller description.
+
+maintainers:
+ - Chen Pei <cp0613@linux.alibaba.com>
+
+properties:
+ compatible:
+ items:
+ - const: riscv_trace,funnel-controller
+ reg:
+ description: A memory region containing registers for funnel controller
+
+ ports:
+ description: Input/Output port definitions
+
+ level:
+ description: Level of the funnel (e.g., 1 means close to the encoder)
+
+additionalProperties: true
+
+examples:
+ - |
+ funnel0: trace_funnel@26404000 {
+ compatible = "riscv_trace,funnel-controller";
+ reg = <0x0 0x26404000 0x0 0x1000>;
+ level = <1>;
+ input_port {
+ port0 {
+ endpoint = <&encoder0>;
+ };
+ };
+ output_port {
+ port0 {
+ endpoint = <&sink0>;
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/riscv/trace/riscv,trace,sink.yaml b/Documentation/devicetree/bindings/riscv/trace/riscv,trace,sink.yaml
new file mode 100644
index 000000000000..b42e65988f31
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/trace/riscv,trace,sink.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/trace/riscv,trace,sink.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RISC-V Trace Sink Controller
+
+description: |
+ riscv trace sink controller description.
+
+maintainers:
+ - Chen Pei <cp0613@linux.alibaba.com>
+
+properties:
+ compatible:
+ items:
+ - const: riscv_trace,sink-controller
+ reg:
+ description: A memory region containing registers for sink controller
+
+ ports:
+ description: Input port definitions
+
+additionalProperties: true
+
+examples:
+ - |
+ sink0: trace_sink@26401000 {
+ compatible = "riscv_trace,sink-controller";
+ reg = <0x0 0x26401000 0x0 0x1000>;
+ input_port {
+ port0 {
+ endpoint = <&funnel0>;
+ };
+ };
+ };
--
2.49.0On 11/09/2025 14:44, cp0613@linux.alibaba.com wrote: > From: Chen Pei <cp0613@linux.alibaba.com> > > This patch has added property definitions related to the riscv Please do not use "This commit/patch/change", but imperative mood. See longer explanation here: https://elixir.bootlin.com/linux/v6.16/source/Documentation/process/submitting-patches.rst#L94 <form letter> Please use scripts/get_maintainers.pl to get a list of necessary people and lists to CC. It might happen, that command when run on an older kernel, gives you outdated entries. Therefore please be sure you base your patches on recent Linux kernel. Tools like b4 or scripts/get_maintainer.pl provide you proper list of people, so fix your workflow. Tools might also fail if you work on some ancient tree (don't, instead use mainline) or work on fork of kernel (don't, instead use mainline). Just use b4 and everything should be fine, although remember about `b4 prep --auto-to-cc` if you added new patches to the patchset. You missed at least devicetree list (maybe more), so this won't be tested by automated tooling. Performing review on untested code might be a waste of time. Please kindly resend and include all necessary To/Cc entries. </form letter> > trace component, providing a foundation for subsequent driver > implementations. > ... > +$id: http://devicetree.org/schemas/riscv/trace/riscv,trace,funnel.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: RISC-V Trace Funnel Controller > + > +description: | > + riscv trace funnel controller description. > + > +maintainers: > + - Chen Pei <cp0613@linux.alibaba.com> > + > +properties: > + compatible: > + items: > + - const: riscv_trace,funnel-controller You need to start following DTS coding style. > + reg: > + description: A memory region containing registers for funnel controller > + > + ports: > + description: Input/Output port definitions > + > + level: > + description: Level of the funnel (e.g., 1 means close to the encoder) > + > +additionalProperties: true No clue from where you got this, but that's not how DT bindings are written. Maybe you used some AI tools for that - in that case, it would be strong grumpy NAK. :( You just waste community time with such approach. Please start from scratch from example-schema or known good bindings. Best regards, Krzysztof
On Thu, 11 Sep 2025 19:24:39 +0200, krzk@kernel.org wrote: > > This patch has added property definitions related to the riscv> > Please do not use "This commit/patch/change", but imperative mood. See > longer explanation here: > https://elixir.bootlin.com/linux/v6.16/source/Documentation/process/submitting-patches.rst#L94> > <form letter> > Please use scripts/get_maintainers.pl to get a list of necessary people > and lists to CC. It might happen, that command when run on an older > kernel, gives you outdated entries. Therefore please be sure you base > your patches on recent Linux kernel.> > Tools like b4 or scripts/get_maintainer.pl provide you proper list of > people, so fix your workflow. Tools might also fail if you work on some > ancient tree (don't, instead use mainline) or work on fork of kernel > (don't, instead use mainline). Just use b4 and everything should be > fine, although remember about `b4 prep --auto-to-cc` if you added new > patches to the patchset.> > You missed at least devicetree list (maybe more), so this won't be > tested by automated tooling. Performing review on untested code might be > a waste of time.> > Please kindly resend and include all necessary To/Cc entries. > </form letter>> > > > trace component, providing a foundation for subsequent driver > > implementations. Thank you very much for your review. My next resend will include all necessary To/Cc entries. >> + items: >> + - const: riscv_trace,funnel-controller> >You need to start following DTS coding style.> > > >> + reg: >> + description: A memory region containing registers for funnel controller Indeed, the current dt-bindings are very primitive and may contain some errors. I should improve and check them before sending them out. I will pay attention to it next time. Thank you, Pei
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