Add Microchip I3C controller

[PATCH 0/4] Add Microchip I3C controller

Posted by Durai Manickam KR 3 weeks, 2 days ago

Add support for microchip SAMA7D65 I3C HCI master only IP. This
hardware is an instance of the MIPI I3C HCI Controller implementing
version 1.0 specification. This driver adds platform-specific
support for SAMA7D65 SoC.

I3C in master mode supports up to 12.5MHz, SDR mode data transfer in
mixed bus mode (I2C and I3C target devices on same i3c bus). It also
supports IBI mechanism.
    
Features tested and supported :
	Standard CCC commands.
       	I3C SDR mode private transfers in PIO mode.
       	I2C transfers in PIO mode.
       	Pure bus mode and mixed bus mode.

Testing done:
With this patch we are able to fully configure the lsm6dso I3C slave
device. Unlike I2C, I hope there is no linux utility to check the
various transactions supported in the host controller. These features
will be added later on this driver after testing (probably with I3C
analyser KIT).

Durai Manickam KR (4):
  clk: at91: sama7d65: add peripheral clock for I3C
  i3c: master: add Microchip SAMA7D65 I3C HCI master driver
  ARM: configs: at91: sama7: Add SAMA7D65 I3C HCI master
  ARM: dts: microchip: add I3C controller

 arch/arm/boot/dts/microchip/sama7d65.dtsi    |   12 +
 arch/arm/configs/sama7_defconfig             |    2 +
 drivers/clk/at91/sama7d65.c                  |    5 +-
 drivers/i3c/master/Kconfig                   |   14 +
 drivers/i3c/master/Makefile                  |    1 +
 drivers/i3c/master/sama7d65-i3c-hci-master.c | 2705 ++++++++++++++++++
 6 files changed, 2737 insertions(+), 2 deletions(-)
 create mode 100644 drivers/i3c/master/sama7d65-i3c-hci-master.c

-- 
2.34.1

Re: [PATCH 0/4] Add Microchip I3C controller

Posted by Conor Dooley 3 weeks, 2 days ago

On Tue, Sep 09, 2025 at 04:43:29PM +0530, Durai Manickam KR wrote:
> Add support for microchip SAMA7D65 I3C HCI master only IP. This
> hardware is an instance of the MIPI I3C HCI Controller implementing
> version 1.0 specification. This driver adds platform-specific
> support for SAMA7D65 SoC.
> 
> I3C in master mode supports up to 12.5MHz, SDR mode data transfer in
> mixed bus mode (I2C and I3C target devices on same i3c bus). It also
> supports IBI mechanism.
>     
> Features tested and supported :
> 	Standard CCC commands.
>        	I3C SDR mode private transfers in PIO mode.
>        	I2C transfers in PIO mode.
>        	Pure bus mode and mixed bus mode.
> 
> Testing done:
> With this patch we are able to fully configure the lsm6dso I3C slave
> device. Unlike I2C, I hope there is no linux utility to check the
> various transactions supported in the host controller. These features
> will be added later on this driver after testing (probably with I3C
> analyser KIT).
> 
> Durai Manickam KR (4):
>   clk: at91: sama7d65: add peripheral clock for I3C
>   i3c: master: add Microchip SAMA7D65 I3C HCI master driver
>   ARM: configs: at91: sama7: Add SAMA7D65 I3C HCI master
>   ARM: dts: microchip: add I3C controller
> 
>  arch/arm/boot/dts/microchip/sama7d65.dtsi    |   12 +
>  arch/arm/configs/sama7_defconfig             |    2 +
>  drivers/clk/at91/sama7d65.c                  |    5 +-
>  drivers/i3c/master/Kconfig                   |   14 +
>  drivers/i3c/master/Makefile                  |    1 +
>  drivers/i3c/master/sama7d65-i3c-hci-master.c | 2705 ++++++++++++++++++
>  6 files changed, 2737 insertions(+), 2 deletions(-)
>  create mode 100644 drivers/i3c/master/sama7d65-i3c-hci-master.c

Where is your dt-binding?

Re: [PATCH 0/4] Add Microchip I3C controller

Posted by Durai.ManickamKR@microchip.com 3 weeks, 1 day ago

On 10/09/25 01:16, Conor Dooley wrote:
> On Tue, Sep 09, 2025 at 04:43:29PM +0530, Durai Manickam KR wrote:
>> Add support for microchip SAMA7D65 I3C HCI master only IP. This
>> hardware is an instance of the MIPI I3C HCI Controller implementing
>> version 1.0 specification. This driver adds platform-specific
>> support for SAMA7D65 SoC.
>>
>> I3C in master mode supports up to 12.5MHz, SDR mode data transfer in
>> mixed bus mode (I2C and I3C target devices on same i3c bus). It also
>> supports IBI mechanism.
>>      
>> Features tested and supported :
>> 	Standard CCC commands.
>>         	I3C SDR mode private transfers in PIO mode.
>>         	I2C transfers in PIO mode.
>>         	Pure bus mode and mixed bus mode.
>>
>> Testing done:
>> With this patch we are able to fully configure the lsm6dso I3C slave
>> device. Unlike I2C, I hope there is no linux utility to check the
>> various transactions supported in the host controller. These features
>> will be added later on this driver after testing (probably with I3C
>> analyser KIT).
>>
>> Durai Manickam KR (4):
>>    clk: at91: sama7d65: add peripheral clock for I3C
>>    i3c: master: add Microchip SAMA7D65 I3C HCI master driver
>>    ARM: configs: at91: sama7: Add SAMA7D65 I3C HCI master
>>    ARM: dts: microchip: add I3C controller
>>
>>   arch/arm/boot/dts/microchip/sama7d65.dtsi    |   12 +
>>   arch/arm/configs/sama7_defconfig             |    2 +
>>   drivers/clk/at91/sama7d65.c                  |    5 +-
>>   drivers/i3c/master/Kconfig                   |   14 +
>>   drivers/i3c/master/Makefile                  |    1 +
>>   drivers/i3c/master/sama7d65-i3c-hci-master.c | 2705 ++++++++++++++++++
>>   6 files changed, 2737 insertions(+), 2 deletions(-)
>>   create mode 100644 drivers/i3c/master/sama7d65-i3c-hci-master.c

Hi Conor,

Was planning to sent along with the review comments received for the i3c 
driver. Will add this and send in patch v2 series.

> Where is your dt-binding?

Re: [PATCH 0/4] Add Microchip I3C controller

Posted by Conor Dooley 3 weeks, 1 day ago

On Wed, Sep 10, 2025 at 06:14:21AM +0000, Durai.ManickamKR@microchip.com wrote:
> On 10/09/25 01:16, Conor Dooley wrote:
> > On Tue, Sep 09, 2025 at 04:43:29PM +0530, Durai Manickam KR wrote:
> >> Add support for microchip SAMA7D65 I3C HCI master only IP. This
> >> hardware is an instance of the MIPI I3C HCI Controller implementing
> >> version 1.0 specification. This driver adds platform-specific
> >> support for SAMA7D65 SoC.
> >>
> >> I3C in master mode supports up to 12.5MHz, SDR mode data transfer in
> >> mixed bus mode (I2C and I3C target devices on same i3c bus). It also
> >> supports IBI mechanism.
> >>      
> >> Features tested and supported :
> >> 	Standard CCC commands.
> >>         	I3C SDR mode private transfers in PIO mode.
> >>         	I2C transfers in PIO mode.
> >>         	Pure bus mode and mixed bus mode.
> >>
> >> Testing done:
> >> With this patch we are able to fully configure the lsm6dso I3C slave
> >> device. Unlike I2C, I hope there is no linux utility to check the
> >> various transactions supported in the host controller. These features
> >> will be added later on this driver after testing (probably with I3C
> >> analyser KIT).
> >>
> >> Durai Manickam KR (4):
> >>    clk: at91: sama7d65: add peripheral clock for I3C
> >>    i3c: master: add Microchip SAMA7D65 I3C HCI master driver
> >>    ARM: configs: at91: sama7: Add SAMA7D65 I3C HCI master
> >>    ARM: dts: microchip: add I3C controller
> >>
> >>   arch/arm/boot/dts/microchip/sama7d65.dtsi    |   12 +
> >>   arch/arm/configs/sama7_defconfig             |    2 +
> >>   drivers/clk/at91/sama7d65.c                  |    5 +-
> >>   drivers/i3c/master/Kconfig                   |   14 +
> >>   drivers/i3c/master/Makefile                  |    1 +
> >>   drivers/i3c/master/sama7d65-i3c-hci-master.c | 2705 ++++++++++++++++++
> >>   6 files changed, 2737 insertions(+), 2 deletions(-)
> >>   create mode 100644 drivers/i3c/master/sama7d65-i3c-hci-master.c
> 
> Hi Conor,
> 
> Was planning to sent along with the review comments received for the i3c 
> driver. Will add this and send in patch v2 series.
> 
> > Where is your dt-binding?

Weird quoting going on here. Why didn't you just send it with the v1,
like is normally done? There's no explanation provided about why you've
omitted it.