[PATCH v6 0/8] Add SBI v3.0 PMU enhancements

Atish Patra posted 8 patches 3 weeks, 2 days ago
arch/riscv/include/asm/kvm_vcpu_pmu.h |   3 +
arch/riscv/include/asm/kvm_vcpu_sbi.h |   2 +-
arch/riscv/include/asm/sbi.h          |  13 +++
arch/riscv/kvm/vcpu_pmu.c             |  74 +++++++++++--
arch/riscv/kvm/vcpu_sbi_pmu.c         |   3 +
arch/riscv/kvm/vcpu_sbi_sta.c         |   9 +-
drivers/perf/riscv_pmu_sbi.c          | 191 +++++++++++++++++++++++++---------
include/linux/perf/riscv_pmu.h        |   1 +
8 files changed, 229 insertions(+), 67 deletions(-)
[PATCH v6 0/8] Add SBI v3.0 PMU enhancements
Posted by Atish Patra 3 weeks, 2 days ago
SBI v3.0 specification[1] added two new improvements to the PMU chaper.
The SBI v3.0 specification is frozen and under public review phase as
per the RISC-V International guidelines. 

1. Added an additional get_event_info function to query event availablity
in bulk instead of individual SBI calls for each event. This helps in
improving the boot time.

2. Raw event width allowed by the platform is widened to have 56 bits
with RAW event v2 as per new clarification in the priv ISA[2].

Apart from implementing these new features, this series improves the gpa
range check in KVM and updates the kvm SBI implementation to SBI v3.0.

The opensbi patches have been merged. This series can be found at [3].

[1] https://github.com/riscv-non-isa/riscv-sbi-doc/releases/download/v3.0-rc7/riscv-sbi.pdf 
[2] https://github.com/riscv/riscv-isa-manual/issues/1578
[3] https://github.com/atishp04/linux/tree/b4/pmu_event_info_v6

Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
Changes in v6:
- Dropped the helper function to check writable slot 
- Updated PATCH 7 to return invalid address error if vcpu_write_guest fails
- Link to v5: https://lore.kernel.org/r/20250829-pmu_event_info-v5-0-9dca26139a33@rivosinc.com

Changes in v5:
- Rebased on top of v6.17-rc3
- Updated PATCH 6 as per feedback to improve the generic helper function
- Adapted PATCH 7 & 8 as per PATCH 6.
- Link to v4: https://lore.kernel.org/r/20250721-pmu_event_info-v4-0-ac76758a4269@rivosinc.com

Changes in v4:
- Rebased on top of v6.16-rc7 
- Fixed a potential compilation issue in PATCH5.
- Minor typos fixed PATCH2 and PATCH3.
- Fixed variable ordering in PATCH6 
- Link to v3: https://lore.kernel.org/r/20250522-pmu_event_info-v3-0-f7bba7fd9cfe@rivosinc.com

Changes in v3:
- Rebased on top of v6.15-rc7 
- Link to v2: https://lore.kernel.org/r/20250115-pmu_event_info-v2-0-84815b70383b@rivosinc.com

Changes in v2:
- Dropped PATCH 2 to be taken during rcX.
- Improved gpa range check validation by introducing a helper function
  and checking the entire range.
- Link to v1: https://lore.kernel.org/r/20241119-pmu_event_info-v1-0-a4f9691421f8@rivosinc.com

---
Atish Patra (8):
      drivers/perf: riscv: Add SBI v3.0 flag
      drivers/perf: riscv: Add raw event v2 support
      RISC-V: KVM: Add support for Raw event v2
      drivers/perf: riscv: Implement PMU event info function
      drivers/perf: riscv: Export PMU event info function
      RISC-V: KVM: No need of explicit writable slot check
      RISC-V: KVM: Implement get event info function
      RISC-V: KVM: Upgrade the supported SBI version to 3.0

 arch/riscv/include/asm/kvm_vcpu_pmu.h |   3 +
 arch/riscv/include/asm/kvm_vcpu_sbi.h |   2 +-
 arch/riscv/include/asm/sbi.h          |  13 +++
 arch/riscv/kvm/vcpu_pmu.c             |  74 +++++++++++--
 arch/riscv/kvm/vcpu_sbi_pmu.c         |   3 +
 arch/riscv/kvm/vcpu_sbi_sta.c         |   9 +-
 drivers/perf/riscv_pmu_sbi.c          | 191 +++++++++++++++++++++++++---------
 include/linux/perf/riscv_pmu.h        |   1 +
 8 files changed, 229 insertions(+), 67 deletions(-)
---
base-commit: e32a80927434907f973f38a88cd19d7e51991d24
change-id: 20241018-pmu_event_info-986e21ce6bd3
--
Regards,
Atish patra
Re: [PATCH v6 0/8] Add SBI v3.0 PMU enhancements
Posted by Paul Walmsley 2 weeks, 3 days ago
On Tue, 9 Sep 2025, Atish Patra wrote:

> SBI v3.0 specification[1] added two new improvements to the PMU chaper.
> The SBI v3.0 specification is frozen and under public review phase as
> per the RISC-V International guidelines. 
> 
> 1. Added an additional get_event_info function to query event availablity
> in bulk instead of individual SBI calls for each event. This helps in
> improving the boot time.
> 
> 2. Raw event width allowed by the platform is widened to have 56 bits
> with RAW event v2 as per new clarification in the priv ISA[2].
> 
> Apart from implementing these new features, this series improves the gpa
> range check in KVM and updates the kvm SBI implementation to SBI v3.0.
> 
> The opensbi patches have been merged. This series can be found at [3].
> 
> [1] https://github.com/riscv-non-isa/riscv-sbi-doc/releases/download/v3.0-rc7/riscv-sbi.pdf 
> [2] https://github.com/riscv/riscv-isa-manual/issues/1578
> [3] https://github.com/atishp04/linux/tree/b4/pmu_event_info_v6
> 
> Signed-off-by: Atish Patra <atishp@rivosinc.com>

For the series:

Acked-by: Paul Walmsley <pjw@kernel.org>


- Paul
Re: [PATCH v6 0/8] Add SBI v3.0 PMU enhancements
Posted by Will Deacon 2 weeks, 3 days ago
On Mon, Sep 15, 2025 at 12:25:52AM -0600, Paul Walmsley wrote:
> On Tue, 9 Sep 2025, Atish Patra wrote:
> 
> > SBI v3.0 specification[1] added two new improvements to the PMU chaper.
> > The SBI v3.0 specification is frozen and under public review phase as
> > per the RISC-V International guidelines. 
> > 
> > 1. Added an additional get_event_info function to query event availablity
> > in bulk instead of individual SBI calls for each event. This helps in
> > improving the boot time.
> > 
> > 2. Raw event width allowed by the platform is widened to have 56 bits
> > with RAW event v2 as per new clarification in the priv ISA[2].
> > 
> > Apart from implementing these new features, this series improves the gpa
> > range check in KVM and updates the kvm SBI implementation to SBI v3.0.
> > 
> > The opensbi patches have been merged. This series can be found at [3].
> > 
> > [1] https://github.com/riscv-non-isa/riscv-sbi-doc/releases/download/v3.0-rc7/riscv-sbi.pdf 
> > [2] https://github.com/riscv/riscv-isa-manual/issues/1578
> > [3] https://github.com/atishp04/linux/tree/b4/pmu_event_info_v6
> > 
> > Signed-off-by: Atish Patra <atishp@rivosinc.com>
> 
> For the series:
> 
> Acked-by: Paul Walmsley <pjw@kernel.org>

I was assuming this series would go via the Risc-V arch tree so please
shout if you were expecting me to take it via drivers/perf/!

Will
Re: [PATCH v6 0/8] Add SBI v3.0 PMU enhancements
Posted by Anup Patel 2 weeks, 3 days ago
Hi Will,

On Mon, Sep 15, 2025 at 4:11 PM Will Deacon <will@kernel.org> wrote:
>
> On Mon, Sep 15, 2025 at 12:25:52AM -0600, Paul Walmsley wrote:
> > On Tue, 9 Sep 2025, Atish Patra wrote:
> >
> > > SBI v3.0 specification[1] added two new improvements to the PMU chaper.
> > > The SBI v3.0 specification is frozen and under public review phase as
> > > per the RISC-V International guidelines.
> > >
> > > 1. Added an additional get_event_info function to query event availablity
> > > in bulk instead of individual SBI calls for each event. This helps in
> > > improving the boot time.
> > >
> > > 2. Raw event width allowed by the platform is widened to have 56 bits
> > > with RAW event v2 as per new clarification in the priv ISA[2].
> > >
> > > Apart from implementing these new features, this series improves the gpa
> > > range check in KVM and updates the kvm SBI implementation to SBI v3.0.
> > >
> > > The opensbi patches have been merged. This series can be found at [3].
> > >
> > > [1] https://github.com/riscv-non-isa/riscv-sbi-doc/releases/download/v3.0-rc7/riscv-sbi.pdf
> > > [2] https://github.com/riscv/riscv-isa-manual/issues/1578
> > > [3] https://github.com/atishp04/linux/tree/b4/pmu_event_info_v6
> > >
> > > Signed-off-by: Atish Patra <atishp@rivosinc.com>
> >
> > For the series:
> >
> > Acked-by: Paul Walmsley <pjw@kernel.org>
>
> I was assuming this series would go via the Risc-V arch tree so please
> shout if you were expecting me to take it via drivers/perf/!
>

Based on offline discussion with Paul, I will take this series
through the KVM RISC-V tree.

Regards,
Anup