The Qualcomm Glymur platform has the new v8 version
of the eDP/DP PHY. So rework the driver to support this
new version and add the platform specific configuration data.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-edp.c | 242 ++++++++++++++++++++++++++++++++++--
1 file changed, 235 insertions(+), 7 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c
index ca9bb9d70e29e1a132bd499fb9f74b5837acf45b..b670cda0fa066d3ff45c66b73cc67e165e55b79a 100644
--- a/drivers/phy/qualcomm/phy-qcom-edp.c
+++ b/drivers/phy/qualcomm/phy-qcom-edp.c
@@ -26,13 +26,15 @@
#include "phy-qcom-qmp-qserdes-com-v4.h"
#include "phy-qcom-qmp-qserdes-com-v6.h"
+#include "phy-qcom-qmp-dp-qserdes-com-v8.h"
+
/* EDP_PHY registers */
#define DP_PHY_CFG 0x0010
#define DP_PHY_CFG_1 0x0014
#define DP_PHY_PD_CTL 0x001c
#define DP_PHY_MODE 0x0020
-#define DP_AUX_CFG_SIZE 10
+#define DP_AUX_CFG_SIZE 13
#define DP_PHY_AUX_CFG(n) (0x24 + (0x04 * (n)))
#define DP_PHY_AUX_INTERRUPT_MASK 0x0058
@@ -76,6 +78,7 @@ struct phy_ver_ops {
int (*com_power_on)(const struct qcom_edp *edp);
int (*com_resetsm_cntrl)(const struct qcom_edp *edp);
int (*com_bias_en_clkbuflr)(const struct qcom_edp *edp);
+ int (*com_clk_fwd_cfg)(const struct qcom_edp *edp);
int (*com_configure_pll)(const struct qcom_edp *edp);
int (*com_configure_ssc)(const struct qcom_edp *edp);
};
@@ -83,6 +86,8 @@ struct phy_ver_ops {
struct qcom_edp_phy_cfg {
bool is_edp;
const u8 *aux_cfg;
+ int aux_cfg_size;
+ const u8 *vco_div_cfg;
const struct qcom_edp_swing_pre_emph_cfg *swing_pre_emph_cfg;
const struct phy_ver_ops *ver_ops;
};
@@ -185,6 +190,10 @@ static const u8 edp_phy_aux_cfg_v4[10] = {
0x00, 0x13, 0x24, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03
};
+static const u8 edp_phy_vco_div_cfg_v4[4] = {
+ 0x1, 0x1, 0x2, 0x0,
+};
+
static const u8 edp_pre_emp_hbr_rbr_v5[4][4] = {
{ 0x05, 0x11, 0x17, 0x1d },
{ 0x05, 0x11, 0x18, 0xff },
@@ -210,6 +219,14 @@ static const u8 edp_phy_aux_cfg_v5[10] = {
0x00, 0x13, 0xa4, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03
};
+static const u8 edp_phy_aux_cfg_v8[13] = {
+ 0x00, 0x00, 0xa0, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03, 0x02, 0x02, 0x4,
+};
+
+static const u8 edp_phy_vco_div_cfg_v8[4] = {
+ 0x1, 0x1, 0x1, 0x1,
+};
+
static int qcom_edp_phy_init(struct phy *phy)
{
struct qcom_edp *edp = phy_get_drvdata(phy);
@@ -224,7 +241,11 @@ static int qcom_edp_phy_init(struct phy *phy)
if (ret)
goto out_disable_supplies;
- memcpy(aux_cfg, edp->cfg->aux_cfg, sizeof(aux_cfg));
+ memcpy(aux_cfg, edp->cfg->aux_cfg, edp->cfg->aux_cfg_size);
+
+ ret = edp->cfg->ver_ops->com_clk_fwd_cfg(edp);
+ if (ret)
+ return ret;
writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
@@ -252,7 +273,7 @@ static int qcom_edp_phy_init(struct phy *phy)
writel(0xfc, edp->edp + DP_PHY_MODE);
- for (int i = 0; i < DP_AUX_CFG_SIZE; i++)
+ for (int i = 0; i < edp->cfg->aux_cfg_size; i++)
writel(aux_cfg[i], edp->edp + DP_PHY_AUX_CFG(i));
writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
@@ -345,22 +366,22 @@ static int qcom_edp_set_vco_div(const struct qcom_edp *edp, unsigned long *pixel
switch (dp_opts->link_rate) {
case 1620:
- vco_div = 0x1;
+ vco_div = edp->cfg->vco_div_cfg[0];
*pixel_freq = 1620000000UL / 2;
break;
case 2700:
- vco_div = 0x1;
+ vco_div = edp->cfg->vco_div_cfg[1];
*pixel_freq = 2700000000UL / 2;
break;
case 5400:
- vco_div = 0x2;
+ vco_div = edp->cfg->vco_div_cfg[2];
*pixel_freq = 5400000000UL / 4;
break;
case 8100:
- vco_div = 0x0;
+ vco_div = edp->cfg->vco_div_cfg[3];
*pixel_freq = 8100000000UL / 6;
break;
@@ -398,6 +419,11 @@ static int qcom_edp_phy_com_resetsm_cntrl_v4(const struct qcom_edp *edp)
val, val & BIT(0), 500, 10000);
}
+static int qcom_edp_com_clk_fwd_cfg_v4(const struct qcom_edp *edp)
+{
+ return 0;
+}
+
static int qcom_edp_com_bias_en_clkbuflr_v4(const struct qcom_edp *edp)
{
/* Turn on BIAS current for PHY/PLL */
@@ -530,6 +556,7 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v4 = {
.com_power_on = qcom_edp_phy_power_on_v4,
.com_resetsm_cntrl = qcom_edp_phy_com_resetsm_cntrl_v4,
.com_bias_en_clkbuflr = qcom_edp_com_bias_en_clkbuflr_v4,
+ .com_clk_fwd_cfg = qcom_edp_com_clk_fwd_cfg_v4,
.com_configure_pll = qcom_edp_com_configure_pll_v4,
.com_configure_ssc = qcom_edp_com_configure_ssc_v4,
};
@@ -537,17 +564,23 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v4 = {
static const struct qcom_edp_phy_cfg sa8775p_dp_phy_cfg = {
.is_edp = false,
.aux_cfg = edp_phy_aux_cfg_v5,
+ .aux_cfg_size = ARRAY_SIZE(edp_phy_aux_cfg_v5),
+ .vco_div_cfg = edp_phy_vco_div_cfg_v4,
.swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg_v5,
.ver_ops = &qcom_edp_phy_ops_v4,
};
static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg = {
.aux_cfg = edp_phy_aux_cfg_v4,
+ .aux_cfg_size = ARRAY_SIZE(edp_phy_aux_cfg_v4),
+ .vco_div_cfg = edp_phy_vco_div_cfg_v4,
.ver_ops = &qcom_edp_phy_ops_v4,
};
static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg = {
.aux_cfg = edp_phy_aux_cfg_v4,
+ .aux_cfg_size = ARRAY_SIZE(edp_phy_aux_cfg_v4),
+ .vco_div_cfg = edp_phy_vco_div_cfg_v4,
.swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg,
.ver_ops = &qcom_edp_phy_ops_v4,
};
@@ -555,6 +588,8 @@ static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg = {
static const struct qcom_edp_phy_cfg sc8280xp_edp_phy_cfg = {
.is_edp = true,
.aux_cfg = edp_phy_aux_cfg_v4,
+ .aux_cfg_size = ARRAY_SIZE(edp_phy_aux_cfg_v4),
+ .vco_div_cfg = edp_phy_vco_div_cfg_v4,
.swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg,
.ver_ops = &qcom_edp_phy_ops_v4,
};
@@ -734,10 +769,202 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v6 = {
static struct qcom_edp_phy_cfg x1e80100_phy_cfg = {
.aux_cfg = edp_phy_aux_cfg_v4,
+ .aux_cfg_size = ARRAY_SIZE(edp_phy_aux_cfg_v4),
+ .vco_div_cfg = edp_phy_vco_div_cfg_v4,
.swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg,
.ver_ops = &qcom_edp_phy_ops_v6,
};
+static int qcom_edp_com_configure_ssc_v8(const struct qcom_edp *edp)
+{
+ const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts;
+ u32 step1;
+ u32 step2;
+
+ switch (dp_opts->link_rate) {
+ case 1620:
+ case 2700:
+ case 8100:
+ step1 = 0x5b;
+ step2 = 0x02;
+ break;
+
+ case 5400:
+ step1 = 0x5b;
+ step2 = 0x02;
+ break;
+
+ default:
+ /* Other link rates aren't supported */
+ return -EINVAL;
+ }
+
+ writel(0x01, edp->pll + DP_QSERDES_V8_COM_SSC_EN_CENTER);
+ writel(0x00, edp->pll + DP_QSERDES_V8_COM_SSC_ADJ_PER1);
+ writel(0x6b, edp->pll + DP_QSERDES_V8_COM_SSC_PER1);
+ writel(0x02, edp->pll + DP_QSERDES_V8_COM_SSC_PER2);
+ writel(step1, edp->pll + DP_QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0);
+ writel(step2, edp->pll + DP_QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0);
+
+ return 0;
+}
+
+static int qcom_edp_com_configure_pll_v8(const struct qcom_edp *edp)
+{
+ const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts;
+ u32 div_frac_start2_mode0;
+ u32 div_frac_start3_mode0;
+ u32 dec_start_mode0;
+ u32 lock_cmp1_mode0;
+ u32 lock_cmp2_mode0;
+ u32 code1_mode0;
+ u32 code2_mode0;
+ u32 hsclk_sel;
+
+ switch (dp_opts->link_rate) {
+ case 1620:
+ hsclk_sel = 0x5;
+ dec_start_mode0 = 0x34;
+ div_frac_start2_mode0 = 0xc0;
+ div_frac_start3_mode0 = 0x0b;
+ lock_cmp1_mode0 = 0x37;
+ lock_cmp2_mode0 = 0x04;
+ code1_mode0 = 0x71;
+ code2_mode0 = 0x0c;
+ break;
+
+ case 2700:
+ hsclk_sel = 0x3;
+ dec_start_mode0 = 0x34;
+ div_frac_start2_mode0 = 0xc0;
+ div_frac_start3_mode0 = 0x0b;
+ lock_cmp1_mode0 = 0x07;
+ lock_cmp2_mode0 = 0x07;
+ code1_mode0 = 0x71;
+ code2_mode0 = 0x0c;
+ break;
+
+ case 5400:
+ hsclk_sel = 0x2;
+ dec_start_mode0 = 0x4f;
+ div_frac_start2_mode0 = 0xa0;
+ div_frac_start3_mode0 = 0x01;
+ lock_cmp1_mode0 = 0x18;
+ lock_cmp2_mode0 = 0x15;
+ code1_mode0 = 0x14;
+ code2_mode0 = 0x25;
+ break;
+
+ case 8100:
+ hsclk_sel = 0x2;
+ dec_start_mode0 = 0x4f;
+ div_frac_start2_mode0 = 0xa0;
+ div_frac_start3_mode0 = 0x01;
+ lock_cmp1_mode0 = 0x18;
+ lock_cmp2_mode0 = 0x15;
+ code1_mode0 = 0x14;
+ code2_mode0 = 0x25;
+ break;
+
+ default:
+ /* Other link rates aren't supported */
+ return -EINVAL;
+ }
+
+ writel(0x01, edp->pll + DP_QSERDES_V8_COM_SVS_MODE_CLK_SEL);
+ writel(0x3b, edp->pll + DP_QSERDES_V8_COM_SYSCLK_EN_SEL);
+ writel(0x02, edp->pll + DP_QSERDES_V8_COM_SYS_CLK_CTRL);
+ writel(0x0c, edp->pll + DP_QSERDES_V8_COM_CLK_ENABLE1);
+ writel(0x06, edp->pll + DP_QSERDES_V8_COM_SYSCLK_BUF_ENABLE);
+ writel(0x30, edp->pll + DP_QSERDES_V8_COM_CLK_SELECT);
+ writel(hsclk_sel, edp->pll + DP_QSERDES_V8_COM_HSCLK_SEL_1);
+ writel(0x07, edp->pll + DP_QSERDES_V8_COM_PLL_IVCO);
+ writel(0x00, edp->pll + DP_QSERDES_V8_COM_LOCK_CMP_EN);
+ writel(0x36, edp->pll + DP_QSERDES_V8_COM_PLL_CCTRL_MODE0);
+ writel(0x16, edp->pll + DP_QSERDES_V8_COM_PLL_RCTRL_MODE0);
+ writel(0x06, edp->pll + DP_QSERDES_V8_COM_CP_CTRL_MODE0);
+ writel(dec_start_mode0, edp->pll + DP_QSERDES_V8_COM_DEC_START_MODE0);
+ writel(0x00, edp->pll + DP_QSERDES_V8_COM_DIV_FRAC_START1_MODE0);
+ writel(div_frac_start2_mode0, edp->pll + DP_QSERDES_V8_COM_DIV_FRAC_START2_MODE0);
+ writel(div_frac_start3_mode0, edp->pll + DP_QSERDES_V8_COM_DIV_FRAC_START3_MODE0);
+ writel(0x96, edp->pll + DP_QSERDES_V8_COM_CMN_CONFIG_1);
+ writel(0x3f, edp->pll + DP_QSERDES_V8_COM_INTEGLOOP_GAIN0_MODE0);
+ writel(0x00, edp->pll + DP_QSERDES_V8_COM_INTEGLOOP_GAIN1_MODE0);
+ writel(0x00, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE_MAP);
+ writel(lock_cmp1_mode0, edp->pll + DP_QSERDES_V8_COM_LOCK_CMP1_MODE0);
+ writel(lock_cmp2_mode0, edp->pll + DP_QSERDES_V8_COM_LOCK_CMP2_MODE0);
+
+ writel(0x0a, edp->pll + DP_QSERDES_V8_COM_BG_TIMER);
+ writel(0x0a, edp->pll + DP_QSERDES_V8_COM_CORECLK_DIV_MODE0);
+ writel(0x00, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE_CTRL);
+ writel(0x1f, edp->pll + DP_QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN);
+ writel(0x00, edp->pll + DP_QSERDES_V8_COM_CORE_CLK_EN);
+ writel(0xa0, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE1_MODE0);
+ writel(0x01, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE2_MODE0);
+
+ writel(code1_mode0, edp->pll + DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0);
+ writel(code2_mode0, edp->pll + DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0);
+
+ return 0;
+}
+
+
+static int qcom_edp_phy_com_resetsm_cntrl_v8(const struct qcom_edp *edp)
+{
+ u32 val;
+
+ writel(0x20, edp->pll + DP_QSERDES_V8_COM_RESETSM_CNTRL);
+
+ return readl_poll_timeout(edp->pll + DP_QSERDES_V8_COM_C_READY_STATUS,
+ val, val & BIT(0), 500, 10000);
+}
+
+static int qcom_edp_com_clk_fwd_cfg_v8(const struct qcom_edp *edp)
+{
+ writel(0x3f, edp->pll + DP_QSERDES_V8_COM_CLK_FWD_CONFIG_1);
+
+ return 0;
+}
+
+static int qcom_edp_com_bias_en_clkbuflr_v8(const struct qcom_edp *edp)
+{
+ /* Turn on BIAS current for PHY/PLL */
+ writel(0x1f, edp->pll + DP_QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN);
+
+ return 0;
+}
+
+static int qcom_edp_phy_power_on_v8(const struct qcom_edp *edp)
+{
+ u32 val;
+
+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
+ DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN |
+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
+ edp->edp + DP_PHY_PD_CTL);
+ writel(0xfc, edp->edp + DP_PHY_MODE);
+
+ return readl_poll_timeout(edp->pll + DP_QSERDES_V8_COM_CMN_STATUS,
+ val, val & BIT(7), 5, 200);
+}
+
+static const struct phy_ver_ops qcom_edp_phy_ops_v8 = {
+ .com_power_on = qcom_edp_phy_power_on_v8,
+ .com_resetsm_cntrl = qcom_edp_phy_com_resetsm_cntrl_v8,
+ .com_bias_en_clkbuflr = qcom_edp_com_bias_en_clkbuflr_v8,
+ .com_clk_fwd_cfg = qcom_edp_com_clk_fwd_cfg_v8,
+ .com_configure_pll = qcom_edp_com_configure_pll_v8,
+ .com_configure_ssc = qcom_edp_com_configure_ssc_v8,
+};
+
+static struct qcom_edp_phy_cfg glymur_phy_cfg = {
+ .aux_cfg = edp_phy_aux_cfg_v8,
+ .aux_cfg_size = ARRAY_SIZE(edp_phy_aux_cfg_v8),
+ .vco_div_cfg = edp_phy_vco_div_cfg_v8,
+ .swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg_v5,
+ .ver_ops = &qcom_edp_phy_ops_v8,
+};
+
static int qcom_edp_phy_power_on(struct phy *phy)
{
const struct qcom_edp *edp = phy_get_drvdata(phy);
@@ -1133,6 +1360,7 @@ static int qcom_edp_phy_probe(struct platform_device *pdev)
}
static const struct of_device_id qcom_edp_phy_match_table[] = {
+ { .compatible = "qcom,glymur-dp-phy", .data = &glymur_phy_cfg, },
{ .compatible = "qcom,sa8775p-edp-phy", .data = &sa8775p_dp_phy_cfg, },
{ .compatible = "qcom,sc7280-edp-phy", .data = &sc7280_dp_phy_cfg, },
{ .compatible = "qcom,sc8180x-edp-phy", .data = &sc7280_dp_phy_cfg, },
--
2.45.2On Tue, Sep 09, 2025 at 01:07:28PM +0300, Abel Vesa wrote:
> The Qualcomm Glymur platform has the new v8 version
> of the eDP/DP PHY. So rework the driver to support this
> new version and add the platform specific configuration data.
>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
> drivers/phy/qualcomm/phy-qcom-edp.c | 242 ++++++++++++++++++++++++++++++++++--
> 1 file changed, 235 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c
> index ca9bb9d70e29e1a132bd499fb9f74b5837acf45b..b670cda0fa066d3ff45c66b73cc67e165e55b79a 100644
> --- a/drivers/phy/qualcomm/phy-qcom-edp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-edp.c
> @@ -26,13 +26,15 @@
> #include "phy-qcom-qmp-qserdes-com-v4.h"
> #include "phy-qcom-qmp-qserdes-com-v6.h"
>
> +#include "phy-qcom-qmp-dp-qserdes-com-v8.h"
> +
> /* EDP_PHY registers */
> #define DP_PHY_CFG 0x0010
> #define DP_PHY_CFG_1 0x0014
> #define DP_PHY_PD_CTL 0x001c
> #define DP_PHY_MODE 0x0020
>
> -#define DP_AUX_CFG_SIZE 10
> +#define DP_AUX_CFG_SIZE 13
If it differs from platform to platform, do we need to continue defining
it?
Also, if the AUX CFG size has increased, didn't it cause other registers
to shift too?
> #define DP_PHY_AUX_CFG(n) (0x24 + (0x04 * (n)))
>
> #define DP_PHY_AUX_INTERRUPT_MASK 0x0058
> @@ -76,6 +78,7 @@ struct phy_ver_ops {
> int (*com_power_on)(const struct qcom_edp *edp);
> int (*com_resetsm_cntrl)(const struct qcom_edp *edp);
> int (*com_bias_en_clkbuflr)(const struct qcom_edp *edp);
> + int (*com_clk_fwd_cfg)(const struct qcom_edp *edp);
> int (*com_configure_pll)(const struct qcom_edp *edp);
> int (*com_configure_ssc)(const struct qcom_edp *edp);
> };
--
With best wishes
Dmitry
On 25-09-09 14:12:46, Dmitry Baryshkov wrote: > On Tue, Sep 09, 2025 at 01:07:28PM +0300, Abel Vesa wrote: > > The Qualcomm Glymur platform has the new v8 version > > of the eDP/DP PHY. So rework the driver to support this > > new version and add the platform specific configuration data. > > > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > > --- > > drivers/phy/qualcomm/phy-qcom-edp.c | 242 ++++++++++++++++++++++++++++++++++-- > > 1 file changed, 235 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c > > index ca9bb9d70e29e1a132bd499fb9f74b5837acf45b..b670cda0fa066d3ff45c66b73cc67e165e55b79a 100644 > > --- a/drivers/phy/qualcomm/phy-qcom-edp.c > > +++ b/drivers/phy/qualcomm/phy-qcom-edp.c > > @@ -26,13 +26,15 @@ > > #include "phy-qcom-qmp-qserdes-com-v4.h" > > #include "phy-qcom-qmp-qserdes-com-v6.h" > > > > +#include "phy-qcom-qmp-dp-qserdes-com-v8.h" > > + > > /* EDP_PHY registers */ > > #define DP_PHY_CFG 0x0010 > > #define DP_PHY_CFG_1 0x0014 > > #define DP_PHY_PD_CTL 0x001c > > #define DP_PHY_MODE 0x0020 > > > > -#define DP_AUX_CFG_SIZE 10 > > +#define DP_AUX_CFG_SIZE 13 > > If it differs from platform to platform, do we need to continue defining > it? > > Also, if the AUX CFG size has increased, didn't it cause other registers > to shift too? AFAICT, all platforms have AUX_CFG0 through AUX_CFG12, we just didn't need to write anything to the last two so far.
On 9/11/25 10:52 AM, Abel Vesa wrote: > On 25-09-09 14:12:46, Dmitry Baryshkov wrote: >> On Tue, Sep 09, 2025 at 01:07:28PM +0300, Abel Vesa wrote: >>> The Qualcomm Glymur platform has the new v8 version >>> of the eDP/DP PHY. So rework the driver to support this >>> new version and add the platform specific configuration data. >>> >>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> >>> --- >>> drivers/phy/qualcomm/phy-qcom-edp.c | 242 ++++++++++++++++++++++++++++++++++-- >>> 1 file changed, 235 insertions(+), 7 deletions(-) >>> >>> diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c >>> index ca9bb9d70e29e1a132bd499fb9f74b5837acf45b..b670cda0fa066d3ff45c66b73cc67e165e55b79a 100644 >>> --- a/drivers/phy/qualcomm/phy-qcom-edp.c >>> +++ b/drivers/phy/qualcomm/phy-qcom-edp.c >>> @@ -26,13 +26,15 @@ >>> #include "phy-qcom-qmp-qserdes-com-v4.h" >>> #include "phy-qcom-qmp-qserdes-com-v6.h" >>> >>> +#include "phy-qcom-qmp-dp-qserdes-com-v8.h" >>> + >>> /* EDP_PHY registers */ >>> #define DP_PHY_CFG 0x0010 >>> #define DP_PHY_CFG_1 0x0014 >>> #define DP_PHY_PD_CTL 0x001c >>> #define DP_PHY_MODE 0x0020 >>> >>> -#define DP_AUX_CFG_SIZE 10 >>> +#define DP_AUX_CFG_SIZE 13 >> >> If it differs from platform to platform, do we need to continue defining >> it? >> >> Also, if the AUX CFG size has increased, didn't it cause other registers >> to shift too? > > AFAICT, all platforms have AUX_CFG0 through AUX_CFG12, we just didn't > need to write anything to the last two so far. I checked 7180/7280/8180/8280/x1e/Glymur and they all do It would make sense to perhaps spell this out explicitly in a separate patch Konrad
On 25-09-11 11:18:53, Konrad Dybcio wrote: > On 9/11/25 10:52 AM, Abel Vesa wrote: > > On 25-09-09 14:12:46, Dmitry Baryshkov wrote: > >> On Tue, Sep 09, 2025 at 01:07:28PM +0300, Abel Vesa wrote: > >>> The Qualcomm Glymur platform has the new v8 version > >>> of the eDP/DP PHY. So rework the driver to support this > >>> new version and add the platform specific configuration data. > >>> > >>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > >>> --- > >>> drivers/phy/qualcomm/phy-qcom-edp.c | 242 ++++++++++++++++++++++++++++++++++-- > >>> 1 file changed, 235 insertions(+), 7 deletions(-) > >>> > >>> diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c > >>> index ca9bb9d70e29e1a132bd499fb9f74b5837acf45b..b670cda0fa066d3ff45c66b73cc67e165e55b79a 100644 > >>> --- a/drivers/phy/qualcomm/phy-qcom-edp.c > >>> +++ b/drivers/phy/qualcomm/phy-qcom-edp.c > >>> @@ -26,13 +26,15 @@ > >>> #include "phy-qcom-qmp-qserdes-com-v4.h" > >>> #include "phy-qcom-qmp-qserdes-com-v6.h" > >>> > >>> +#include "phy-qcom-qmp-dp-qserdes-com-v8.h" > >>> + > >>> /* EDP_PHY registers */ > >>> #define DP_PHY_CFG 0x0010 > >>> #define DP_PHY_CFG_1 0x0014 > >>> #define DP_PHY_PD_CTL 0x001c > >>> #define DP_PHY_MODE 0x0020 > >>> > >>> -#define DP_AUX_CFG_SIZE 10 > >>> +#define DP_AUX_CFG_SIZE 13 > >> > >> If it differs from platform to platform, do we need to continue defining > >> it? > >> > >> Also, if the AUX CFG size has increased, didn't it cause other registers > >> to shift too? > > > > AFAICT, all platforms have AUX_CFG0 through AUX_CFG12, we just didn't > > need to write anything to the last two so far. > > I checked 7180/7280/8180/8280/x1e/Glymur and they all do > > It would make sense to perhaps spell this out explicitly in a separate > patch Makes sense. Will do. Thanks.
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