From: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
To support the DWC ECAM mechanism, prepare the driver by performing below
configurations:
1. Since the ELBI region will be covered by the ECAM 'config' space,
override the 'elbi_base' with the address derived from 'dbi_base' and
the offset from PARF_SLV_DBI_ELBI register.
2. Block the transactions from the host bridge to devices other than Root
Port on the root bus to return all F's. This is required when the 'CFG
Shift Feature' of iATU is enabled.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
[mani: code split, reworded subject/description and comments]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
---
drivers/pci/controller/dwc/pcie-qcom.c | 69 ++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 5092752de23866ef95036bb3f8fae9bb06e8ea1e..4324555de72adbdd3dcdf59497f9bd067d9c90ab 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -55,6 +55,7 @@
#define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8
#define PARF_Q2A_FLUSH 0x1ac
#define PARF_LTSSM 0x1b0
+#define PARF_SLV_DBI_ELBI 0x1b4
#define PARF_INT_ALL_STATUS 0x224
#define PARF_INT_ALL_CLEAR 0x228
#define PARF_INT_ALL_MASK 0x22c
@@ -64,6 +65,16 @@
#define PARF_DBI_BASE_ADDR_V2_HI 0x354
#define PARF_SLV_ADDR_SPACE_SIZE_V2 0x358
#define PARF_SLV_ADDR_SPACE_SIZE_V2_HI 0x35c
+#define PARF_BLOCK_SLV_AXI_WR_BASE 0x360
+#define PARF_BLOCK_SLV_AXI_WR_BASE_HI 0x364
+#define PARF_BLOCK_SLV_AXI_WR_LIMIT 0x368
+#define PARF_BLOCK_SLV_AXI_WR_LIMIT_HI 0x36c
+#define PARF_BLOCK_SLV_AXI_RD_BASE 0x370
+#define PARF_BLOCK_SLV_AXI_RD_BASE_HI 0x374
+#define PARF_BLOCK_SLV_AXI_RD_LIMIT 0x378
+#define PARF_BLOCK_SLV_AXI_RD_LIMIT_HI 0x37c
+#define PARF_ECAM_BASE 0x380
+#define PARF_ECAM_BASE_HI 0x384
#define PARF_NO_SNOOP_OVERRIDE 0x3d4
#define PARF_ATU_BASE_ADDR 0x634
#define PARF_ATU_BASE_ADDR_HI 0x638
@@ -87,6 +98,7 @@
/* PARF_SYS_CTRL register fields */
#define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29)
+#define PCIE_ECAM_BLOCKER_EN BIT(26)
#define MST_WAKEUP_EN BIT(13)
#define SLV_WAKEUP_EN BIT(12)
#define MSTR_ACLK_CGC_DIS BIT(10)
@@ -134,6 +146,9 @@
/* PARF_LTSSM register fields */
#define LTSSM_EN BIT(8)
+/* PARF_SLV_DBI_ELBI */
+#define SLV_DBI_ELBI_ADDR_BASE GENMASK(11, 0)
+
/* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */
#define PARF_INT_ALL_LINK_UP BIT(13)
#define PARF_INT_MSI_DEV_0_7 GENMASK(30, 23)
@@ -317,6 +332,47 @@ static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
qcom_perst_assert(pcie, false);
}
+static void qcom_pci_config_ecam(struct dw_pcie_rp *pp)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct qcom_pcie *pcie = to_qcom_pcie(pci);
+ u64 addr, addr_end;
+ u32 val;
+
+ writel_relaxed(lower_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE);
+ writel_relaxed(upper_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE_HI);
+
+ /*
+ * The only device on root bus is a single Root Port. So if PCI core
+ * tries to access any devices other than Device/Function (0.0) in Bus
+ * 0, the TLP will go outside of the controller to the PCI bus. But with
+ * CFG Shift Feature (ECAM) enabled in iATU, there is no guarantee that
+ * the response is going to be all F's. Hence, to make sure that the
+ * requester gets all F's response for accesses other than the Root
+ * Port, configure iATU to block the transactions starting from function
+ * 1 of the root bus to the end of the root bus (i.e from dbi_base + 4kb
+ * to dbi_base + 1MB).
+ */
+ addr = pci->dbi_phys_addr + SZ_4K;
+ writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE);
+ writel_relaxed(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE_HI);
+
+ writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE);
+ writel_relaxed(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE_HI);
+
+ addr_end = pci->dbi_phys_addr + SZ_1M - 1;
+
+ writel_relaxed(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT);
+ writel_relaxed(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT_HI);
+
+ writel_relaxed(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT);
+ writel_relaxed(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT_HI);
+
+ val = readl_relaxed(pcie->parf + PARF_SYS_CTRL);
+ val |= PCIE_ECAM_BLOCKER_EN;
+ writel_relaxed(val, pcie->parf + PARF_SYS_CTRL);
+}
+
static int qcom_pcie_start_link(struct dw_pcie *pci)
{
struct qcom_pcie *pcie = to_qcom_pcie(pci);
@@ -326,6 +382,9 @@ static int qcom_pcie_start_link(struct dw_pcie *pci)
qcom_pcie_common_set_16gt_lane_margining(pci);
}
+ if (pci->pp.ecam_enabled)
+ qcom_pci_config_ecam(&pci->pp);
+
/* Enable Link Training state machine */
if (pcie->cfg->ops->ltssm_enable)
pcie->cfg->ops->ltssm_enable(pcie);
@@ -1314,6 +1373,7 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct qcom_pcie *pcie = to_qcom_pcie(pci);
+ u16 offset;
int ret;
qcom_ep_reset_assert(pcie);
@@ -1322,6 +1382,15 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp)
if (ret)
return ret;
+ if (pp->ecam_enabled) {
+ /*
+ * Override ELBI when ECAM is enabled, as when ECAM is enabled,
+ * ELBI moves under the 'config' space.
+ */
+ offset = FIELD_GET(SLV_DBI_ELBI_ADDR_BASE, readl(pcie->parf + PARF_SLV_DBI_ELBI));
+ pci->elbi_base = pci->dbi_base + offset;
+ }
+
ret = qcom_pcie_phy_power_on(pcie);
if (ret)
goto err_deinit;
--
2.45.2On Tue, Sep 09, 2025 at 12:37:52PM +0530, Manivannan Sadhasivam wrote:
> From: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
>
> To support the DWC ECAM mechanism, prepare the driver by performing below
> configurations:
>
> 1. Since the ELBI region will be covered by the ECAM 'config' space,
> override the 'elbi_base' with the address derived from 'dbi_base' and
> the offset from PARF_SLV_DBI_ELBI register.
>
> 2. Block the transactions from the host bridge to devices other than Root
> Port on the root bus to return all F's. This is required when the 'CFG
> Shift Feature' of iATU is enabled.
FWIW, before I noticed your v9, I had updated the comments here to fix
a few inconsistencies. Here's the diff:
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 7c2b2c8c61c2..962f0311a23a 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -343,15 +343,15 @@ static void qcom_pci_config_ecam(struct dw_pcie_rp *pp)
writel_relaxed(upper_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE_HI);
/*
- * The only device on root bus is a single Root Port. So if PCI core
- * tries to access any devices other than Device/Function (0.0) in Bus
- * 0, the TLP will go outside of the controller to the PCI bus. But with
- * CFG Shift Feature (ECAM) enabled in iATU, there is no guarantee that
- * the response is going to be all F's. Hence, to make sure that the
+ * The only device on the root bus is a single Root Port. If we try to
+ * access any devices other than Device/Function 00.0 on Bus 0, the TLP
+ * will go outside of the controller to the PCI bus. But with CFG Shift
+ * Feature (ECAM) enabled in iATU, there is no guarantee that the
+ * response is going to be all F's. Hence, to make sure that the
* requester gets all F's response for accesses other than the Root
- * Port, configure iATU to block the transactions starting from function
- * 1 of the root bus to the end of the root bus (i.e from dbi_base + 4kb
- * to dbi_base + 1MB).
+ * Port, configure iATU to block the transactions starting from
+ * function 1 of the root bus to the end of the root bus (i.e., from
+ * dbi_base + 4KB to dbi_base + 1MB).
*/
addr = pci->dbi_phys_addr + SZ_4K;
writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE);
@@ -1385,7 +1385,7 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp)
if (pp->ecam_enabled) {
/*
* Override ELBI when ECAM is enabled, as when ECAM
- * is enabled ELBI moves along with the dbi config space.
+ * is enabled ELBI moves along with the DBI config space.
*/
offset = FIELD_GET(SLV_DBI_ELBI_ADDR_BASE, readl(pcie->parf + PARF_SLV_DBI_ELBI));
pci->elbi_base = pci->dbi_base + offset;
On Fri, Sep 12, 2025 at 04:50:53PM GMT, Bjorn Helgaas wrote:
> On Tue, Sep 09, 2025 at 12:37:52PM +0530, Manivannan Sadhasivam wrote:
> > From: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> >
> > To support the DWC ECAM mechanism, prepare the driver by performing below
> > configurations:
> >
> > 1. Since the ELBI region will be covered by the ECAM 'config' space,
> > override the 'elbi_base' with the address derived from 'dbi_base' and
> > the offset from PARF_SLV_DBI_ELBI register.
> >
> > 2. Block the transactions from the host bridge to devices other than Root
> > Port on the root bus to return all F's. This is required when the 'CFG
> > Shift Feature' of iATU is enabled.
>
> FWIW, before I noticed your v9, I had updated the comments here to fix
> a few inconsistencies. Here's the diff:
>
I will incorporate this in next version.
- Mani
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 7c2b2c8c61c2..962f0311a23a 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -343,15 +343,15 @@ static void qcom_pci_config_ecam(struct dw_pcie_rp *pp)
> writel_relaxed(upper_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE_HI);
>
> /*
> - * The only device on root bus is a single Root Port. So if PCI core
> - * tries to access any devices other than Device/Function (0.0) in Bus
> - * 0, the TLP will go outside of the controller to the PCI bus. But with
> - * CFG Shift Feature (ECAM) enabled in iATU, there is no guarantee that
> - * the response is going to be all F's. Hence, to make sure that the
> + * The only device on the root bus is a single Root Port. If we try to
> + * access any devices other than Device/Function 00.0 on Bus 0, the TLP
> + * will go outside of the controller to the PCI bus. But with CFG Shift
> + * Feature (ECAM) enabled in iATU, there is no guarantee that the
> + * response is going to be all F's. Hence, to make sure that the
> * requester gets all F's response for accesses other than the Root
> - * Port, configure iATU to block the transactions starting from function
> - * 1 of the root bus to the end of the root bus (i.e from dbi_base + 4kb
> - * to dbi_base + 1MB).
> + * Port, configure iATU to block the transactions starting from
> + * function 1 of the root bus to the end of the root bus (i.e., from
> + * dbi_base + 4KB to dbi_base + 1MB).
> */
> addr = pci->dbi_phys_addr + SZ_4K;
> writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE);
> @@ -1385,7 +1385,7 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp)
> if (pp->ecam_enabled) {
> /*
> * Override ELBI when ECAM is enabled, as when ECAM
> - * is enabled ELBI moves along with the dbi config space.
> + * is enabled ELBI moves along with the DBI config space.
> */
> offset = FIELD_GET(SLV_DBI_ELBI_ADDR_BASE, readl(pcie->parf + PARF_SLV_DBI_ELBI));
> pci->elbi_base = pci->dbi_base + offset;
--
மணிவண்ணன் சதாசிவம்
Sorry, I missed your repost of this series, Mani. I'll reiterate my
questions here.
I also deleted the pci/controller/dwc-ecam branch, where Krishna's v8
series was queued up, to avoid confusion (it looked like that branch
was ready to be included in linux-next, but it's not).
On Tue, Sep 09, 2025 at 12:37:52PM +0530, Manivannan Sadhasivam wrote:
> From: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
>
> To support the DWC ECAM mechanism, prepare the driver by performing below
> configurations:
>
> 1. Since the ELBI region will be covered by the ECAM 'config' space,
> override the 'elbi_base' with the address derived from 'dbi_base' and
> the offset from PARF_SLV_DBI_ELBI register.
>
> 2. Block the transactions from the host bridge to devices other than Root
> Port on the root bus to return all F's. This is required when the 'CFG
> Shift Feature' of iATU is enabled.
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> +static void qcom_pci_config_ecam(struct dw_pcie_rp *pp)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct qcom_pcie *pcie = to_qcom_pcie(pci);
> + u64 addr, addr_end;
> + u32 val;
> +
> + writel_relaxed(lower_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE);
> + writel_relaxed(upper_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE_HI);
> +
> + /*
> + * The only device on root bus is a single Root Port. So if PCI core
> + * tries to access any devices other than Device/Function (0.0) in Bus
> + * 0, the TLP will go outside of the controller to the PCI bus. But with
> + * CFG Shift Feature (ECAM) enabled in iATU, there is no guarantee that
> + * the response is going to be all F's. Hence, to make sure that the
> + * requester gets all F's response for accesses other than the Root
> + * Port, configure iATU to block the transactions starting from function
> + * 1 of the root bus to the end of the root bus (i.e from dbi_base + 4kb
> + * to dbi_base + 1MB).
> + */
> + addr = pci->dbi_phys_addr + SZ_4K;
> + writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE);
> + writel_relaxed(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE_HI);
> +
> + writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE);
> + writel_relaxed(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE_HI);
> +
> + addr_end = pci->dbi_phys_addr + SZ_1M - 1;
> +
> + writel_relaxed(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT);
> + writel_relaxed(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT_HI);
> +
> + writel_relaxed(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT);
> + writel_relaxed(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT_HI);
> +
> + val = readl_relaxed(pcie->parf + PARF_SYS_CTRL);
> + val |= PCIE_ECAM_BLOCKER_EN;
> + writel_relaxed(val, pcie->parf + PARF_SYS_CTRL);
The driver already supported ECAM in the existing "firmware_managed"
path (which looks untouched by this series and doesn't do any of this
iATU configuration).
And IIUC, this series adds support for ECAM whenever the DT 'config'
range is sufficiently aligned. In this new ECAM support, it looks
like we look for and pay attention to 'bus-range' in this path:
qcom_pcie_probe
dw_pcie_host_init
devm_pci_alloc_host_bridge
devm_of_pci_bridge_init
pci_parse_request_of_pci_ranges
devm_of_pci_get_host_bridge_resources
of_pci_parse_bus_range
of_property_read_u32_array(node, "bus-range", ...)
dw_pcie_host_get_resources
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config")
pp->ecam_enabled = dw_pcie_ecam_enabled(pp, res)
Since qcom_pci_config_ecam() doesn't look at the root bus number at
all, is this also an implicit restriction that the root bus must be
bus 0? Does qcom support root buses other than 0?
> +}
> +
> static int qcom_pcie_start_link(struct dw_pcie *pci)
> {
> struct qcom_pcie *pcie = to_qcom_pcie(pci);
> @@ -326,6 +382,9 @@ static int qcom_pcie_start_link(struct dw_pcie *pci)
> qcom_pcie_common_set_16gt_lane_margining(pci);
> }
>
> + if (pci->pp.ecam_enabled)
> + qcom_pci_config_ecam(&pci->pp);
qcom_pcie_start_link() seems like a strange place to do this
ECAM-related iATU configuration. ECAM is a function of the host
bridge, not of any particular Root Port or link.
> /* Enable Link Training state machine */
> if (pcie->cfg->ops->ltssm_enable)
> pcie->cfg->ops->ltssm_enable(pcie);
On Fri, Sep 12, 2025 at 04:44:32PM GMT, Bjorn Helgaas wrote:
> Sorry, I missed your repost of this series, Mani. I'll reiterate my
> questions here.
>
> I also deleted the pci/controller/dwc-ecam branch, where Krishna's v8
> series was queued up, to avoid confusion (it looked like that branch
> was ready to be included in linux-next, but it's not).
>
> On Tue, Sep 09, 2025 at 12:37:52PM +0530, Manivannan Sadhasivam wrote:
> > From: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> >
> > To support the DWC ECAM mechanism, prepare the driver by performing below
> > configurations:
> >
> > 1. Since the ELBI region will be covered by the ECAM 'config' space,
> > override the 'elbi_base' with the address derived from 'dbi_base' and
> > the offset from PARF_SLV_DBI_ELBI register.
> >
> > 2. Block the transactions from the host bridge to devices other than Root
> > Port on the root bus to return all F's. This is required when the 'CFG
> > Shift Feature' of iATU is enabled.
>
> > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>
> > +static void qcom_pci_config_ecam(struct dw_pcie_rp *pp)
> > +{
> > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > + struct qcom_pcie *pcie = to_qcom_pcie(pci);
> > + u64 addr, addr_end;
> > + u32 val;
> > +
> > + writel_relaxed(lower_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE);
> > + writel_relaxed(upper_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE_HI);
> > +
> > + /*
> > + * The only device on root bus is a single Root Port. So if PCI core
> > + * tries to access any devices other than Device/Function (0.0) in Bus
> > + * 0, the TLP will go outside of the controller to the PCI bus. But with
> > + * CFG Shift Feature (ECAM) enabled in iATU, there is no guarantee that
> > + * the response is going to be all F's. Hence, to make sure that the
> > + * requester gets all F's response for accesses other than the Root
> > + * Port, configure iATU to block the transactions starting from function
> > + * 1 of the root bus to the end of the root bus (i.e from dbi_base + 4kb
> > + * to dbi_base + 1MB).
> > + */
> > + addr = pci->dbi_phys_addr + SZ_4K;
> > + writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE);
> > + writel_relaxed(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE_HI);
> > +
> > + writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE);
> > + writel_relaxed(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE_HI);
> > +
> > + addr_end = pci->dbi_phys_addr + SZ_1M - 1;
> > +
> > + writel_relaxed(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT);
> > + writel_relaxed(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT_HI);
> > +
> > + writel_relaxed(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT);
> > + writel_relaxed(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT_HI);
> > +
> > + val = readl_relaxed(pcie->parf + PARF_SYS_CTRL);
> > + val |= PCIE_ECAM_BLOCKER_EN;
> > + writel_relaxed(val, pcie->parf + PARF_SYS_CTRL);
>
> The driver already supported ECAM in the existing "firmware_managed"
> path (which looks untouched by this series and doesn't do any of this
> iATU configuration).
>
'firmware_managed' refers to the Qcom platforms supporting BIOS/bootloader that
has initialized the PCIe controller and configured ECAM mode. The driver doesn't
need to do any resource handling on its own including iATU as everything would
be handled by the BIOS/bootloader. This mode is used by the Qcom Automotive
SoCs.
And This mode is different from the DWC ECAM mode implemented in this series as
this one requires doing all iATU configuration in the driver itself. This mode
will be used by the Mobile/IoT/Compute SoCs.
Qcom SoCs have different requirement for different market segments. This is the
reason why we have many different implementations.
> And IIUC, this series adds support for ECAM whenever the DT 'config'
> range is sufficiently aligned. In this new ECAM support, it looks
> like we look for and pay attention to 'bus-range' in this path:
>
> qcom_pcie_probe
> dw_pcie_host_init
> devm_pci_alloc_host_bridge
> devm_of_pci_bridge_init
> pci_parse_request_of_pci_ranges
> devm_of_pci_get_host_bridge_resources
> of_pci_parse_bus_range
> of_property_read_u32_array(node, "bus-range", ...)
> dw_pcie_host_get_resources
> res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config")
> pp->ecam_enabled = dw_pcie_ecam_enabled(pp, res)
>
> Since qcom_pci_config_ecam() doesn't look at the root bus number at
> all, is this also an implicit restriction that the root bus must be
> bus 0? Does qcom support root buses other than 0?
>
No, not at the moment.
> > +}
> > +
> > static int qcom_pcie_start_link(struct dw_pcie *pci)
> > {
> > struct qcom_pcie *pcie = to_qcom_pcie(pci);
> > @@ -326,6 +382,9 @@ static int qcom_pcie_start_link(struct dw_pcie *pci)
> > qcom_pcie_common_set_16gt_lane_margining(pci);
> > }
> >
> > + if (pci->pp.ecam_enabled)
> > + qcom_pci_config_ecam(&pci->pp);
>
> qcom_pcie_start_link() seems like a strange place to do this
> ECAM-related iATU configuration. ECAM is a function of the host
> bridge, not of any particular Root Port or link.
>
I thought qcom_pci_config_ecam() needs to be called after
dw_pcie_config_ecam_iatu() and before pci_host_probe() in dw_pcie_host_init().
Since there were no other callbacks in-between other than this start_link()
callback, Krishna has called it from here.
But looks like qcom_pci_config_ecam() could be called before
dw_pcie_config_ecam_iatu() as replied by Krishna [1]. So I will move it to
qcom_pcie_host_init().
- Mani
[1] https://lore.kernel.org/linux-pci/d12e002b-e99e-4963-a732-4873e13c5419@oss.qualcomm.com
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