Set the CR4.MCE bit as the last step during init. This brings the MCA
init flow closer to what is described in the x86 docs.

x86 docs:
	AMD		Intel
			MCG_CTL
	MCA_CONFIG	MCG_EXT_CTL
	MCi_CTL		MCi_CTL
	MCG_CTL
	CR4.MCE		CR4.MCE

Current Linux:
	AMD		Intel
	CR4.MCE		CR4.MCE
	MCG_CTL		MCG_CTL
	MCA_CONFIG	MCG_EXT_CTL
	MCi_CTL		MCi_CTL

Updated Linux:
	AMD		Intel
	MCG_CTL		MCG_CTL
	MCA_CONFIG	MCG_EXT_CTL
	MCi_CTL		MCi_CTL
	CR4.MCE		CR4.MCE

The new init flow will match Intel's docs, but there will still be a
mismatch for AMD regarding MCG_CTL. However, there is no known issue
with this ordering, so leave it for now.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---

Notes:
    Link:
    https://lore.kernel.org/r/20250825-wip-mca-updates-v5-7-865768a2eef8@amd.com
    
    v5->v6:
    * Only move CR4.MCE programming.
    * Update commit message to match the new change.
    
    v4->v5:
    * New in v5.

 arch/x86/kernel/cpu/mce/core.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 0326fbb83adc..9e31834b3542 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1850,8 +1850,6 @@ static void __mcheck_cpu_init_generic(void)
 {
 	u64 cap;
 
-	cr4_set_bits(X86_CR4_MCE);
-
 	rdmsrq(MSR_IA32_MCG_CAP, cap);
 	if (cap & MCG_CTL_P)
 		wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
@@ -2276,6 +2274,7 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c)
 	__mcheck_cpu_init_vendor(c);
 	__mcheck_cpu_init_prepare_banks();
 	__mcheck_cpu_setup_timer();
+	cr4_set_bits(X86_CR4_MCE);
 }
 
 /*
@@ -2443,6 +2442,7 @@ static void mce_syscore_resume(void)
 	__mcheck_cpu_init_generic();
 	__mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info));
 	__mcheck_cpu_init_prepare_banks();
+	cr4_set_bits(X86_CR4_MCE);
 }
 
 static struct syscore_ops mce_syscore_ops = {
@@ -2462,6 +2462,7 @@ static void mce_cpu_restart(void *data)
 	__mcheck_cpu_init_generic();
 	__mcheck_cpu_init_prepare_banks();
 	__mcheck_cpu_init_timer();
+	cr4_set_bits(X86_CR4_MCE);
 }
 
 /* Reinit MCEs after user configuration changes */

-- 
2.51.0