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[PATCH v2 1/2] arm64: dts: ti: k3-j721e-main: Update DSS EDP integration configuration register

Harikrishna Shenoy posted 2 patches 3 months, 1 week ago
[PATCH v2 1/2] arm64: dts: ti: k3-j721e-main: Update DSS EDP integration configuration register
Posted by Harikrishna Shenoy 3 months, 1 week ago 
Fix size of DSS_EDP0_INT_CFG_VP to 256B as stated in
TRM Table 2-1 MAIN Domain Memory Map.
Link: https://www.ti.com/lit/zip/spruil1/SPRUIL_DRA829_TDA4VM

Fixes: 92c996f4ceab ("arm64: dts: ti: k3-j721e-*: add DP & DP PHY")
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Signed-off-by: Harikrishna Shenoy <h-shenoy@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index ab3666ff4297..3fa7537d5414 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -1863,7 +1863,7 @@ mhdp: dp-bridge@a000000 {
 		 * the PHY driver.
 		 */
 		reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
-		      <0x00 0x04f40000 0x00 0x20>;    /* DSS_EDP0_INTG_CFG_VP */
+		      <0x00 0x04f40000 0x00 0x100>;    /* DSS_EDP0_INTG_CFG_VP */
 		reg-names = "mhdptx", "j721e-intg";
 
 		clocks = <&k3_clks 151 36>;
-- 
2.34.1
Re: [PATCH v2 1/2] arm64: dts: ti: k3-j721e-main: Update DSS EDP integration configuration register
Posted by Tomi Valkeinen 3 months, 1 week ago 
Hi,

On 07/09/2025 21:28, Harikrishna Shenoy wrote:
> Fix size of DSS_EDP0_INT_CFG_VP to 256B as stated in
> TRM Table 2-1 MAIN Domain Memory Map.
> Link: https://www.ti.com/lit/zip/spruil1/SPRUIL_DRA829_TDA4VM

What issues does this cause?

 Tomi

> Fixes: 92c996f4ceab ("arm64: dts: ti: k3-j721e-*: add DP & DP PHY")
> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
> Signed-off-by: Harikrishna Shenoy <h-shenoy@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> index ab3666ff4297..3fa7537d5414 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> @@ -1863,7 +1863,7 @@ mhdp: dp-bridge@a000000 {
>  		 * the PHY driver.
>  		 */
>  		reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
> -		      <0x00 0x04f40000 0x00 0x20>;    /* DSS_EDP0_INTG_CFG_VP */
> +		      <0x00 0x04f40000 0x00 0x100>;    /* DSS_EDP0_INTG_CFG_VP */
>  		reg-names = "mhdptx", "j721e-intg";
>  
>  		clocks = <&k3_clks 151 36>;
Re: [PATCH v2 1/2] arm64: dts: ti: k3-j721e-main: Update DSS EDP integration configuration register
Posted by Harikrishna Shenoy 3 months, 1 week ago 
On 9/8/25 11:46, Tomi Valkeinen wrote:
> Hi,
>
> On 07/09/2025 21:28, Harikrishna Shenoy wrote:
>> Fix size of DSS_EDP0_INT_CFG_VP to 256B as stated in
>> TRM Table 2-1 MAIN Domain Memory Map.
>> Link: https://www.ti.com/lit/zip/spruil1/SPRUIL_DRA829_TDA4VM
> What issues does this cause?
>
>   Tomi

Hi Tomi,

No issues seen in driver functionality yet, but it might when we enable 
HDCP,MST which driver supports but not enabled yet.

so thought it is better to align as per TRM, hence aligning the size as 
per TRM.

>> Fixes: 92c996f4ceab ("arm64: dts: ti: k3-j721e-*: add DP & DP PHY")
>> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
>> Signed-off-by: Harikrishna Shenoy <h-shenoy@ti.com>
>> ---
>>   arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> index ab3666ff4297..3fa7537d5414 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> @@ -1863,7 +1863,7 @@ mhdp: dp-bridge@a000000 {
>>   		 * the PHY driver.
>>   		 */
>>   		reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
>> -		      <0x00 0x04f40000 0x00 0x20>;    /* DSS_EDP0_INTG_CFG_VP */
>> +		      <0x00 0x04f40000 0x00 0x100>;    /* DSS_EDP0_INTG_CFG_VP */
>>   		reg-names = "mhdptx", "j721e-intg";
>>   
>>   		clocks = <&k3_clks 151 36>;
Re: [PATCH v2 1/2] arm64: dts: ti: k3-j721e-main: Update DSS EDP integration configuration register
Posted by Tomi Valkeinen 3 months, 1 week ago 
On 08/09/2025 09:20, Harikrishna Shenoy wrote:
> 
> On 9/8/25 11:46, Tomi Valkeinen wrote:
>> Hi,
>>
>> On 07/09/2025 21:28, Harikrishna Shenoy wrote:
>>> Fix size of DSS_EDP0_INT_CFG_VP to 256B as stated in
>>> TRM Table 2-1 MAIN Domain Memory Map.
>>> Link: https://www.ti.com/lit/zip/spruil1/SPRUIL_DRA829_TDA4VM
>> What issues does this cause?
>>
>>   Tomi
> 
> Hi Tomi,
> 
> No issues seen in driver functionality yet, but it might when we enable
> HDCP,MST which driver supports but not enabled yet.
> 
> so thought it is better to align as per TRM, hence aligning the size as
> per TRM.

You need to explain this in the patch message. What is the current
behavior/issue, how does this fix it, what are the effects, etc...

Also, here I think it's good to consider what this means for the future
HDCP, MST work you refer to. Is HDCP/MST just adding driver code, no new
DT properties or such needed? If so, what happens when a user runs the
new code with the old dtb, which contains a too small register range?

 Tomi

> 
>>> Fixes: 92c996f4ceab ("arm64: dts: ti: k3-j721e-*: add DP & DP PHY")
>>> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
>>> Signed-off-by: Harikrishna Shenoy <h-shenoy@ti.com>
>>> ---
>>>   arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 +-
>>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/
>>> boot/dts/ti/k3-j721e-main.dtsi
>>> index ab3666ff4297..3fa7537d5414 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>> @@ -1863,7 +1863,7 @@ mhdp: dp-bridge@a000000 {
>>>            * the PHY driver.
>>>            */
>>>           reg = <0x00 0x0a000000 0x00 0x030a00>, /*
>>> DSS_EDP0_V2A_CORE_VP_REGS_APB */
>>> -              <0x00 0x04f40000 0x00 0x20>;    /*
>>> DSS_EDP0_INTG_CFG_VP */
>>> +              <0x00 0x04f40000 0x00 0x100>;    /*
>>> DSS_EDP0_INTG_CFG_VP */
>>>           reg-names = "mhdptx", "j721e-intg";
>>>             clocks = <&k3_clks 151 36>;
Re: [PATCH v2 1/2] arm64: dts: ti: k3-j721e-main: Update DSS EDP integration configuration register
Posted by Kumar, Udit 3 months, 1 week ago 
On 9/8/2025 11:58 AM, Tomi Valkeinen wrote:
> On 08/09/2025 09:20, Harikrishna Shenoy wrote:
>> On 9/8/25 11:46, Tomi Valkeinen wrote:
>>> Hi,
>>>
>>> On 07/09/2025 21:28, Harikrishna Shenoy wrote:
>>>> Fix size of DSS_EDP0_INT_CFG_VP to 256B as stated in
>>>> TRM Table 2-1 MAIN Domain Memory Map.
>>>> Link: https://www.ti.com/lit/zip/spruil1/SPRUIL_DRA829_TDA4VM
>>> What issues does this cause?
>>>
>>>    Tomi
>> Hi Tomi,
>>
>> No issues seen in driver functionality yet, but it might when we enable
>> HDCP,MST which driver supports but not enabled yet.
>>
>> so thought it is better to align as per TRM, hence aligning the size as
>> per TRM.
> You need to explain this in the patch message. What is the current
> behavior/issue, how does this fix it, what are the effects, etc...
>
> Also, here I think it's good to consider what this means for the future
> HDCP, MST work you refer to. Is HDCP/MST just adding driver code, no new
> DT properties or such needed? If so, what happens when a user runs the
> new code with the old dtb, which contains a too small register range?


we can keep to 256 bytes for completeness, but i don't think registers 
are defined beyond 0x20.


>
>   Tomi
>
>>>> Fixes: 92c996f4ceab ("arm64: dts: ti: k3-j721e-*: add DP & DP PHY")
>>>> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
>>>> Signed-off-by: Harikrishna Shenoy <h-shenoy@ti.com>
>>>> ---
>>>>    arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 +-
>>>>    1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/
>>>> boot/dts/ti/k3-j721e-main.dtsi
>>>> index ab3666ff4297..3fa7537d5414 100644
>>>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>>> @@ -1863,7 +1863,7 @@ mhdp: dp-bridge@a000000 {
>>>>             * the PHY driver.
>>>>             */
>>>>            reg = <0x00 0x0a000000 0x00 0x030a00>, /*
>>>> DSS_EDP0_V2A_CORE_VP_REGS_APB */
>>>> -              <0x00 0x04f40000 0x00 0x20>;    /*
>>>> DSS_EDP0_INTG_CFG_VP */
>>>> +              <0x00 0x04f40000 0x00 0x100>;    /*
>>>> DSS_EDP0_INTG_CFG_VP */
>>>>            reg-names = "mhdptx", "j721e-intg";
>>>>              clocks = <&k3_clks 151 36>;
Re: [PATCH v2 1/2] arm64: dts: ti: k3-j721e-main: Update DSS EDP integration configuration register
Posted by Beleswar Prasad Padhi 3 months, 1 week ago 
On 07/09/25 23:58, Harikrishna Shenoy wrote:
> Fix size of DSS_EDP0_INT_CFG_VP to 256B as stated in
> TRM Table 2-1 MAIN Domain Memory Map.
> Link: https://www.ti.com/lit/zip/spruil1/SPRUIL_DRA829_TDA4VM


Gives a 404 on the above link?

Thanks,
Beleswar

>
> Fixes: 92c996f4ceab ("arm64: dts: ti: k3-j721e-*: add DP & DP PHY")
> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
> Signed-off-by: Harikrishna Shenoy <h-shenoy@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> index ab3666ff4297..3fa7537d5414 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> @@ -1863,7 +1863,7 @@ mhdp: dp-bridge@a000000 {
>  		 * the PHY driver.
>  		 */
>  		reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
> -		      <0x00 0x04f40000 0x00 0x20>;    /* DSS_EDP0_INTG_CFG_VP */
> +		      <0x00 0x04f40000 0x00 0x100>;    /* DSS_EDP0_INTG_CFG_VP */
>  		reg-names = "mhdptx", "j721e-intg";
>  
>  		clocks = <&k3_clks 151 36>;
Re: [PATCH v2 1/2] arm64: dts: ti: k3-j721e-main: Update DSS EDP integration configuration register
Posted by Harikrishna Shenoy 3 months, 1 week ago 
On 9/8/25 10:04, Beleswar Prasad Padhi wrote:
> On 07/09/25 23:58, Harikrishna Shenoy wrote:
>> Fix size of DSS_EDP0_INT_CFG_VP to 256B as stated in
>> TRM Table 2-1 MAIN Domain Memory Map.
>> Link: https://www.ti.com/lit/zip/spruil1/SPRUIL_DRA829_TDA4VM
>
> Gives a 404 on the above link?

https://www.ti.com/lit/zip/spruil1 this downalods the zip, refer SPRUIL_DRA829_TDA4VM file.

>
> Thanks,
> Beleswar
>
>> Fixes: 92c996f4ceab ("arm64: dts: ti: k3-j721e-*: add DP & DP PHY")
>> Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
>> Signed-off-by: Harikrishna Shenoy <h-shenoy@ti.com>
>> ---
>>   arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> index ab3666ff4297..3fa7537d5414 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> @@ -1863,7 +1863,7 @@ mhdp: dp-bridge@a000000 {
>>   		 * the PHY driver.
>>   		 */
>>   		reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
>> -		      <0x00 0x04f40000 0x00 0x20>;    /* DSS_EDP0_INTG_CFG_VP */
>> +		      <0x00 0x04f40000 0x00 0x100>;    /* DSS_EDP0_INTG_CFG_VP */
>>   		reg-names = "mhdptx", "j721e-intg";
>>   
>>   		clocks = <&k3_clks 151 36>;

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