The Mali-based GPU on the MediaTek MT8196 SoC is shackled to its concept
of "MFlexGraphics", which in this iteration includes an embedded MCU
that needs to be poked to power on the GPU, and is in charge of
controlling all the clocks and regulators.
In return, it lets us omit the OPP tables from the device tree, as those
can now be enumerated at runtime from the MCU.
Add the mediatek,mt8196-mali compatible, and a performance-controller
property which points to a node representing such setups. It's required
on mt8196 devices.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
.../bindings/gpu/arm,mali-valhall-csf.yaml | 36 +++++++++++++++++++++-
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
index a5b4e00217587c5d1f889094e2fff7b76e6148eb..6df802e900b744d226395c29f8d87fb6d3282d26 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
@@ -19,6 +19,7 @@ properties:
- items:
- enum:
- rockchip,rk3588-mali
+ - mediatek,mt8196-mali
- const: arm,mali-valhall-csf # Mali Valhall GPU model/revision is fully discoverable
reg:
@@ -53,6 +54,13 @@ properties:
opp-table:
type: object
+ performance-controller:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ A phandle of a device that controls this GPU's power and frequency,
+ if any. If present, this is usually in the form of some specialised
+ embedded MCU.
+
power-domains:
minItems: 1
maxItems: 5
@@ -91,7 +99,6 @@ required:
- interrupts
- interrupt-names
- clocks
- - mali-supply
additionalProperties: false
@@ -105,9 +112,24 @@ allOf:
properties:
clocks:
minItems: 3
+ performance-controller: false
power-domains:
maxItems: 1
power-domain-names: false
+ required:
+ - mali-supply
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,mt8196-mali
+ then:
+ properties:
+ mali-supply: false
+ sram-supply: false
+ operating-points-v2: false
+ required:
+ - performance-controller
examples:
- |
@@ -143,5 +165,17 @@ examples:
};
};
};
+ - |
+ gpu2: gpu@48000000 {
+ compatible = "mediatek,mt8196-mali", "arm,mali-valhall-csf";
+ reg = <0x48000000 0x480000>;
+ clocks = <&mfgpll 0>;
+ clock-names = "core";
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "job", "mmu", "gpu";
+ performance-controller = <&gpufreq>;
+ };
...
--
2.51.0On Fri, Sep 05, 2025 at 12:22:57PM +0200, Nicolas Frattaroli wrote:
> The Mali-based GPU on the MediaTek MT8196 SoC is shackled to its concept
> of "MFlexGraphics", which in this iteration includes an embedded MCU
> that needs to be poked to power on the GPU, and is in charge of
> controlling all the clocks and regulators.
>
> In return, it lets us omit the OPP tables from the device tree, as those
> can now be enumerated at runtime from the MCU.
>
> Add the mediatek,mt8196-mali compatible, and a performance-controller
> property which points to a node representing such setups. It's required
> on mt8196 devices.
>
> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
> ---
> .../bindings/gpu/arm,mali-valhall-csf.yaml | 36 +++++++++++++++++++++-
> 1 file changed, 35 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
> index a5b4e00217587c5d1f889094e2fff7b76e6148eb..6df802e900b744d226395c29f8d87fb6d3282d26 100644
> --- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
> @@ -19,6 +19,7 @@ properties:
> - items:
> - enum:
> - rockchip,rk3588-mali
> + - mediatek,mt8196-mali
> - const: arm,mali-valhall-csf # Mali Valhall GPU model/revision is fully discoverable
>
> reg:
> @@ -53,6 +54,13 @@ properties:
> opp-table:
> type: object
>
> + performance-controller:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + A phandle of a device that controls this GPU's power and frequency,
> + if any. If present, this is usually in the form of some specialised
> + embedded MCU.
> +
> power-domains:
> minItems: 1
> maxItems: 5
> @@ -91,7 +99,6 @@ required:
> - interrupts
> - interrupt-names
> - clocks
> - - mali-supply
>
> additionalProperties: false
>
> @@ -105,9 +112,24 @@ allOf:
> properties:
> clocks:
> minItems: 3
> + performance-controller: false
> power-domains:
> maxItems: 1
> power-domain-names: false
> + required:
> + - mali-supply
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: rockchip,mt8196-mali
s/rockchip/mediatek/
Best regards,
Liviu
> + then:
> + properties:
> + mali-supply: false
> + sram-supply: false
> + operating-points-v2: false
> + required:
> + - performance-controller
>
> examples:
> - |
> @@ -143,5 +165,17 @@ examples:
> };
> };
> };
> + - |
> + gpu2: gpu@48000000 {
> + compatible = "mediatek,mt8196-mali", "arm,mali-valhall-csf";
> + reg = <0x48000000 0x480000>;
> + clocks = <&mfgpll 0>;
> + clock-names = "core";
> + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH 0>;
> + interrupt-names = "job", "mmu", "gpu";
> + performance-controller = <&gpufreq>;
> + };
>
> ...
>
> --
> 2.51.0
>
--
====================
| I would like to |
| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---------------
¯\_(ツ)_/¯
On Fri, Sep 05, 2025 at 12:22:57PM +0200, Nicolas Frattaroli wrote: > The Mali-based GPU on the MediaTek MT8196 SoC is shackled to its concept > of "MFlexGraphics", which in this iteration includes an embedded MCU > that needs to be poked to power on the GPU, and is in charge of > controlling all the clocks and regulators. > > In return, it lets us omit the OPP tables from the device tree, as those > can now be enumerated at runtime from the MCU. > > Add the mediatek,mt8196-mali compatible, and a performance-controller > property which points to a node representing such setups. It's required > on mt8196 devices. > > Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> > --- > .../bindings/gpu/arm,mali-valhall-csf.yaml | 36 +++++++++++++++++++++- > 1 file changed, 35 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml > index a5b4e00217587c5d1f889094e2fff7b76e6148eb..6df802e900b744d226395c29f8d87fb6d3282d26 100644 > --- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml > @@ -19,6 +19,7 @@ properties: > - items: > - enum: > - rockchip,rk3588-mali > + - mediatek,mt8196-mali > - const: arm,mali-valhall-csf # Mali Valhall GPU model/revision is fully discoverable > > reg: > @@ -53,6 +54,13 @@ properties: > opp-table: > type: object > > + performance-controller: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + A phandle of a device that controls this GPU's power and frequency, > + if any. If present, this is usually in the form of some specialised > + embedded MCU. We already abuse power-domains binding with both power and performance. There's a performance-domain binding too, but only used on one platform for CPUs (Mediatek too IIRC). Or perhaps you could just point to an empty OPP table. I don't think you have anything new here, so don't invent something new. Rob
Hi Rob, On Saturday, 6 September 2025 01:26:57 Central European Summer Time Rob Herring wrote: > On Fri, Sep 05, 2025 at 12:22:57PM +0200, Nicolas Frattaroli wrote: > > The Mali-based GPU on the MediaTek MT8196 SoC is shackled to its concept > > of "MFlexGraphics", which in this iteration includes an embedded MCU > > that needs to be poked to power on the GPU, and is in charge of > > controlling all the clocks and regulators. > > > > In return, it lets us omit the OPP tables from the device tree, as those > > can now be enumerated at runtime from the MCU. > > > > Add the mediatek,mt8196-mali compatible, and a performance-controller > > property which points to a node representing such setups. It's required > > on mt8196 devices. > > > > Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> > > --- > > .../bindings/gpu/arm,mali-valhall-csf.yaml | 36 +++++++++++++++++++++- > > 1 file changed, 35 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml > > index a5b4e00217587c5d1f889094e2fff7b76e6148eb..6df802e900b744d226395c29f8d87fb6d3282d26 100644 > > --- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml > > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml > > @@ -19,6 +19,7 @@ properties: > > - items: > > - enum: > > - rockchip,rk3588-mali > > + - mediatek,mt8196-mali > > - const: arm,mali-valhall-csf # Mali Valhall GPU model/revision is fully discoverable > > > > reg: > > @@ -53,6 +54,13 @@ properties: > > opp-table: > > type: object > > > > + performance-controller: > > + $ref: /schemas/types.yaml#/definitions/phandle > > + description: > > + A phandle of a device that controls this GPU's power and frequency, > > + if any. If present, this is usually in the form of some specialised > > + embedded MCU. > > We already abuse power-domains binding with both power and performance. > There's a performance-domain binding too, but only used on one platform > for CPUs (Mediatek too IIRC). Or perhaps you could just point to an > empty OPP table. I don't think you have anything new here, so don't > invent something new. Oops, yeah, I forgot about performance-domain already existing. I agree that it looks like a good fit; iirc I initially disregarded it because I thought it was an actual heterogenous core cpufreq-y thing I'd be overloading with new meaning, but I see now that this is not so, and aside from mediatek, Apple appears to be the only user. Thanks for the fast review. Kind regards, Nicolas Frattaroli > > Rob >
© 2016 - 2025 Red Hat, Inc.