From: Chuan Liu <chuan.liu@amlogic.com>
Add video encoder, demodulator and CVBS clocks.
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
drivers/clk/meson/s4-peripherals.c | 203 +++++++++++++++++++++++++++++++++++++
1 file changed, 203 insertions(+)
diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peripherals.c
index 6d69b132d1e1..c0f877ce0993 100644
--- a/drivers/clk/meson/s4-peripherals.c
+++ b/drivers/clk/meson/s4-peripherals.c
@@ -44,6 +44,7 @@
#define CLKCTRL_VDIN_MEAS_CLK_CTRL 0x0f8
#define CLKCTRL_VAPBCLK_CTRL 0x0fc
#define CLKCTRL_HDCP22_CTRL 0x100
+#define CLKCTRL_CDAC_CLK_CTRL 0x108
#define CLKCTRL_VDEC_CLK_CTRL 0x140
#define CLKCTRL_VDEC2_CLK_CTRL 0x144
#define CLKCTRL_VDEC3_CLK_CTRL 0x148
@@ -1126,6 +1127,22 @@ static struct clk_regmap s4_cts_encp_sel = {
},
};
+static struct clk_regmap s4_cts_encl_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = CLKCTRL_VIID_CLK_DIV,
+ .mask = 0xf,
+ .shift = 12,
+ .table = mux_table_cts_sel,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "cts_encl_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_hws = s4_cts_parent_hws,
+ .num_parents = ARRAY_SIZE(s4_cts_parent_hws),
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
static struct clk_regmap s4_cts_vdac_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = CLKCTRL_VIID_CLK_DIV,
@@ -1205,6 +1222,22 @@ static struct clk_regmap s4_cts_encp = {
},
};
+static struct clk_regmap s4_cts_encl = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = CLKCTRL_VID_CLK_CTRL2,
+ .bit_idx = 3,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "cts_encl",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &s4_cts_encl_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
static struct clk_regmap s4_cts_vdac = {
.data = &(struct clk_regmap_gate_data){
.offset = CLKCTRL_VID_CLK_CTRL2,
@@ -2735,6 +2768,165 @@ static struct clk_regmap s4_gen_clk = {
},
};
+/* CVBS DAC */
+static struct clk_regmap s4_cdac_sel = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_CDAC_CLK_CTRL,
+ .mask = 0x3,
+ .shift = 16,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "cdac_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "xtal", },
+ { .fw_name = "fclk_div5" },
+ },
+ .num_parents = 2,
+ },
+};
+
+static struct clk_regmap s4_cdac_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_CDAC_CLK_CTRL,
+ .shift = 0,
+ .width = 16,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "cdac_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &s4_cdac_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap s4_cdac = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_CDAC_CLK_CTRL,
+ .bit_idx = 20,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "cdac",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &s4_cdac_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap s4_demod_core_sel = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_DEMOD_CLK_CTRL,
+ .mask = 0x3,
+ .shift = 9,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "demod_core_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "xtal" },
+ { .fw_name = "fclk_div7" },
+ { .fw_name = "fclk_div4" }
+ },
+ .num_parents = 3,
+ },
+};
+
+static struct clk_regmap s4_demod_core_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_DEMOD_CLK_CTRL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "demod_core_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &s4_demod_core_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap s4_demod_core = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_DEMOD_CLK_CTRL,
+ .bit_idx = 8
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "demod_core",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &s4_demod_core_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+/* CVBS ADC */
+static struct clk_regmap s4_adc_extclk_in_sel = {
+ .data = &(struct clk_regmap_mux_data) {
+ .offset = CLKCTRL_DEMOD_CLK_CTRL,
+ .mask = 0x7,
+ .shift = 25,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "adc_extclk_in_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "xtal" },
+ { .fw_name = "fclk_div4" },
+ { .fw_name = "fclk_div3" },
+ { .fw_name = "fclk_div5" },
+ { .fw_name = "fclk_div7" },
+ { .fw_name = "mpll2" },
+ { .fw_name = "gp0_pll" },
+ { .fw_name = "hifi_pll" }
+ },
+ .num_parents = 8,
+ },
+};
+
+static struct clk_regmap s4_adc_extclk_in_div = {
+ .data = &(struct clk_regmap_div_data) {
+ .offset = CLKCTRL_DEMOD_CLK_CTRL,
+ .shift = 16,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "adc_extclk_in_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &s4_adc_extclk_in_sel.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap s4_adc_extclk_in = {
+ .data = &(struct clk_regmap_gate_data) {
+ .offset = CLKCTRL_DEMOD_CLK_CTRL,
+ .bit_idx = 24
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "adc_extclk_in",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &s4_adc_extclk_in_div.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
static const struct clk_parent_data s4_pclk_parents = { .hw = &s4_sys_clk.hw };
#define S4_PCLK(_name, _reg, _bit, _flags) \
@@ -3028,6 +3220,17 @@ static struct clk_hw *s4_peripherals_hw_clks[] = {
[CLKID_HDCP22_SKPCLK_SEL] = &s4_hdcp22_skpclk_sel.hw,
[CLKID_HDCP22_SKPCLK_DIV] = &s4_hdcp22_skpclk_div.hw,
[CLKID_HDCP22_SKPCLK] = &s4_hdcp22_skpclk.hw,
+ [CLKID_CTS_ENCL_SEL] = &s4_cts_encl_sel.hw,
+ [CLKID_CTS_ENCL] = &s4_cts_encl.hw,
+ [CLKID_CDAC_SEL] = &s4_cdac_sel.hw,
+ [CLKID_CDAC_DIV] = &s4_cdac_div.hw,
+ [CLKID_CDAC] = &s4_cdac.hw,
+ [CLKID_DEMOD_CORE_SEL] = &s4_demod_core_sel.hw,
+ [CLKID_DEMOD_CORE_DIV] = &s4_demod_core_div.hw,
+ [CLKID_DEMOD_CORE] = &s4_demod_core.hw,
+ [CLKID_ADC_EXTCLK_IN_SEL] = &s4_adc_extclk_in_sel.hw,
+ [CLKID_ADC_EXTCLK_IN_DIV] = &s4_adc_extclk_in_div.hw,
+ [CLKID_ADC_EXTCLK_IN] = &s4_adc_extclk_in.hw,
};
static const struct meson_clkc_data s4_peripherals_clkc_data = {
--
2.42.0Hi Chuan,
kernel test robot noticed the following build errors:
[auto build test ERROR on 01f3a6d1d59b8e25a6de243b0d73075cf0415eaf]
url: https://github.com/intel-lab-lkp/linux/commits/Chuan-Liu-via-B4-Relay/dt-bindings-clock-add-video-clock-indices-for-Amlogic-S4-SoC/20250905-171121
base: 01f3a6d1d59b8e25a6de243b0d73075cf0415eaf
patch link: https://lore.kernel.org/r/20250905-add_video_clk-v3-2-8304c91b8b94%40amlogic.com
patch subject: [PATCH v3 2/2] clk: amlogic: add video-related clocks for S4 SoC
config: arm64-randconfig-002-20250906 (https://download.01.org/0day-ci/archive/20250906/202509061948.3VcIfqLx-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 12.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250906/202509061948.3VcIfqLx-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202509061948.3VcIfqLx-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/clk/meson/s4-peripherals.c:1135:26: error: 'mux_table_cts_sel' undeclared here (not in a function)
1135 | .table = mux_table_cts_sel,
| ^~~~~~~~~~~~~~~~~
>> drivers/clk/meson/s4-peripherals.c:1140:31: error: 's4_cts_parent_hws' undeclared here (not in a function); did you mean 's4_cts_parents'?
1140 | .parent_hws = s4_cts_parent_hws,
| ^~~~~~~~~~~~~~~~~
| s4_cts_parents
In file included from include/linux/build_bug.h:5,
from include/linux/bits.h:30,
from include/linux/bitops.h:6,
from include/linux/of.h:15,
from include/linux/clk-provider.h:9,
from drivers/clk/meson/s4-peripherals.c:9:
include/linux/compiler.h:197:82: error: expression in static assertion is not an integer
197 | #define __BUILD_BUG_ON_ZERO_MSG(e, msg, ...) ((int)sizeof(struct {_Static_assert(!(e), msg);}))
| ^
include/linux/compiler.h:202:33: note: in expansion of macro '__BUILD_BUG_ON_ZERO_MSG'
202 | #define __must_be_array(a) __BUILD_BUG_ON_ZERO_MSG(!__is_array(a), \
| ^~~~~~~~~~~~~~~~~~~~~~~
include/linux/array_size.h:11:59: note: in expansion of macro '__must_be_array'
11 | #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr))
| ^~~~~~~~~~~~~~~
drivers/clk/meson/s4-peripherals.c:1141:32: note: in expansion of macro 'ARRAY_SIZE'
1141 | .num_parents = ARRAY_SIZE(s4_cts_parent_hws),
| ^~~~~~~~~~
vim +/mux_table_cts_sel +1135 drivers/clk/meson/s4-peripherals.c
1129
1130 static struct clk_regmap s4_cts_encl_sel = {
1131 .data = &(struct clk_regmap_mux_data){
1132 .offset = CLKCTRL_VIID_CLK_DIV,
1133 .mask = 0xf,
1134 .shift = 12,
> 1135 .table = mux_table_cts_sel,
1136 },
1137 .hw.init = &(struct clk_init_data){
1138 .name = "cts_encl_sel",
1139 .ops = &clk_regmap_mux_ops,
> 1140 .parent_hws = s4_cts_parent_hws,
1141 .num_parents = ARRAY_SIZE(s4_cts_parent_hws),
1142 .flags = CLK_SET_RATE_PARENT,
1143 },
1144 };
1145
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi Krzysztof:
Sorry, I forgot to add your 'Acked-by' tag in this version.
Please ignore this patch for now. I will re-add it in the next revision.
On 9/5/2025 5:06 PM, Chuan Liu via B4 Relay wrote:
> [ EXTERNAL EMAIL ]
>
> From: Chuan Liu<chuan.liu@amlogic.com>
>
> Add video encoder, demodulator and CVBS clocks.
>
> Signed-off-by: Chuan Liu<chuan.liu@amlogic.com>
> ---
> drivers/clk/meson/s4-peripherals.c | 203 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 203 insertions(+)
>
> diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peripherals.c
> index 6d69b132d1e1..c0f877ce0993 100644
> --- a/drivers/clk/meson/s4-peripherals.c
> +++ b/drivers/clk/meson/s4-peripherals.c
> @@ -44,6 +44,7 @@
> #define CLKCTRL_VDIN_MEAS_CLK_CTRL 0x0f8
> #define CLKCTRL_VAPBCLK_CTRL 0x0fc
> #define CLKCTRL_HDCP22_CTRL 0x100
> +#define CLKCTRL_CDAC_CLK_CTRL 0x108
> #define CLKCTRL_VDEC_CLK_CTRL 0x140
> #define CLKCTRL_VDEC2_CLK_CTRL 0x144
> #define CLKCTRL_VDEC3_CLK_CTRL 0x148
> @@ -1126,6 +1127,22 @@ static struct clk_regmap s4_cts_encp_sel = {
> },
> };
>
> +static struct clk_regmap s4_cts_encl_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = CLKCTRL_VIID_CLK_DIV,
> + .mask = 0xf,
> + .shift = 12,
> + .table = mux_table_cts_sel,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "cts_encl_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_hws = s4_cts_parent_hws,
> + .num_parents = ARRAY_SIZE(s4_cts_parent_hws),
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> static struct clk_regmap s4_cts_vdac_sel = {
> .data = &(struct clk_regmap_mux_data){
> .offset = CLKCTRL_VIID_CLK_DIV,
> @@ -1205,6 +1222,22 @@ static struct clk_regmap s4_cts_encp = {
> },
> };
>
> +static struct clk_regmap s4_cts_encl = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = CLKCTRL_VID_CLK_CTRL2,
> + .bit_idx = 3,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "cts_encl",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_cts_encl_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> static struct clk_regmap s4_cts_vdac = {
> .data = &(struct clk_regmap_gate_data){
> .offset = CLKCTRL_VID_CLK_CTRL2,
> @@ -2735,6 +2768,165 @@ static struct clk_regmap s4_gen_clk = {
> },
> };
>
> +/* CVBS DAC */
> +static struct clk_regmap s4_cdac_sel = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = CLKCTRL_CDAC_CLK_CTRL,
> + .mask = 0x3,
> + .shift = 16,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "cdac_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = (const struct clk_parent_data []) {
> + { .fw_name = "xtal", },
> + { .fw_name = "fclk_div5" },
> + },
> + .num_parents = 2,
> + },
> +};
> +
> +static struct clk_regmap s4_cdac_div = {
> + .data = &(struct clk_regmap_div_data) {
> + .offset = CLKCTRL_CDAC_CLK_CTRL,
> + .shift = 0,
> + .width = 16,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "cdac_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_cdac_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap s4_cdac = {
> + .data = &(struct clk_regmap_gate_data) {
> + .offset = CLKCTRL_CDAC_CLK_CTRL,
> + .bit_idx = 20,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "cdac",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_cdac_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap s4_demod_core_sel = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = CLKCTRL_DEMOD_CLK_CTRL,
> + .mask = 0x3,
> + .shift = 9,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "demod_core_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = (const struct clk_parent_data []) {
> + { .fw_name = "xtal" },
> + { .fw_name = "fclk_div7" },
> + { .fw_name = "fclk_div4" }
> + },
> + .num_parents = 3,
> + },
> +};
> +
> +static struct clk_regmap s4_demod_core_div = {
> + .data = &(struct clk_regmap_div_data) {
> + .offset = CLKCTRL_DEMOD_CLK_CTRL,
> + .shift = 0,
> + .width = 7,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "demod_core_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_demod_core_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap s4_demod_core = {
> + .data = &(struct clk_regmap_gate_data) {
> + .offset = CLKCTRL_DEMOD_CLK_CTRL,
> + .bit_idx = 8
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "demod_core",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_demod_core_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +/* CVBS ADC */
> +static struct clk_regmap s4_adc_extclk_in_sel = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = CLKCTRL_DEMOD_CLK_CTRL,
> + .mask = 0x7,
> + .shift = 25,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "adc_extclk_in_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_data = (const struct clk_parent_data []) {
> + { .fw_name = "xtal" },
> + { .fw_name = "fclk_div4" },
> + { .fw_name = "fclk_div3" },
> + { .fw_name = "fclk_div5" },
> + { .fw_name = "fclk_div7" },
> + { .fw_name = "mpll2" },
> + { .fw_name = "gp0_pll" },
> + { .fw_name = "hifi_pll" }
> + },
> + .num_parents = 8,
> + },
> +};
> +
> +static struct clk_regmap s4_adc_extclk_in_div = {
> + .data = &(struct clk_regmap_div_data) {
> + .offset = CLKCTRL_DEMOD_CLK_CTRL,
> + .shift = 16,
> + .width = 7,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "adc_extclk_in_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_adc_extclk_in_sel.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap s4_adc_extclk_in = {
> + .data = &(struct clk_regmap_gate_data) {
> + .offset = CLKCTRL_DEMOD_CLK_CTRL,
> + .bit_idx = 24
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "adc_extclk_in",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_adc_extclk_in_div.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> static const struct clk_parent_data s4_pclk_parents = { .hw = &s4_sys_clk.hw };
>
> #define S4_PCLK(_name, _reg, _bit, _flags) \
> @@ -3028,6 +3220,17 @@ static struct clk_hw *s4_peripherals_hw_clks[] = {
> [CLKID_HDCP22_SKPCLK_SEL] = &s4_hdcp22_skpclk_sel.hw,
> [CLKID_HDCP22_SKPCLK_DIV] = &s4_hdcp22_skpclk_div.hw,
> [CLKID_HDCP22_SKPCLK] = &s4_hdcp22_skpclk.hw,
> + [CLKID_CTS_ENCL_SEL] = &s4_cts_encl_sel.hw,
> + [CLKID_CTS_ENCL] = &s4_cts_encl.hw,
> + [CLKID_CDAC_SEL] = &s4_cdac_sel.hw,
> + [CLKID_CDAC_DIV] = &s4_cdac_div.hw,
> + [CLKID_CDAC] = &s4_cdac.hw,
> + [CLKID_DEMOD_CORE_SEL] = &s4_demod_core_sel.hw,
> + [CLKID_DEMOD_CORE_DIV] = &s4_demod_core_div.hw,
> + [CLKID_DEMOD_CORE] = &s4_demod_core.hw,
> + [CLKID_ADC_EXTCLK_IN_SEL] = &s4_adc_extclk_in_sel.hw,
> + [CLKID_ADC_EXTCLK_IN_DIV] = &s4_adc_extclk_in_div.hw,
> + [CLKID_ADC_EXTCLK_IN] = &s4_adc_extclk_in.hw,
> };
>
> static const struct meson_clkc_data s4_peripherals_clkc_data = {
>
> --
> 2.42.0
>
>
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