From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Move the hardcoded switch mode mask definition into the SoC-specific
miic_of_data structure. This allows each SoC to define its own mask
value rather than relying on a single fixed constant. For RZ/N1 the
mask remains GENMASK(4, 0).
This is in preparation for adding support for RZ/T2H, where the
switch mode mask is GENMASK(2, 0).
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
- No change.
---
drivers/net/pcs/pcs-rzn1-miic.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-miic.c
index c119ec66fe95..c0aa93fd7274 100644
--- a/drivers/net/pcs/pcs-rzn1-miic.c
+++ b/drivers/net/pcs/pcs-rzn1-miic.c
@@ -7,6 +7,7 @@
#include <linux/array_size.h>
#include <linux/bits.h>
+#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/mdio.h>
@@ -23,7 +24,6 @@
#define MIIC_ESID_CODE 0x4
#define MIIC_MODCTRL 0x8
-#define MIIC_MODCTRL_SW_MODE GENMASK(4, 0)
#define MIIC_CONVCTRL(port) (0x100 + (port) * 4)
@@ -146,6 +146,7 @@ struct miic {
* @index_to_string_count: Number of entries in the index_to_string array
* @miic_port_start: MIIC port start number
* @miic_port_max: Maximum MIIC supported
+ * @sw_mode_mask: Switch mode mask
*/
struct miic_of_data {
struct modctrl_match *match_table;
@@ -157,6 +158,7 @@ struct miic_of_data {
u8 index_to_string_count;
u8 miic_port_start;
u8 miic_port_max;
+ u8 sw_mode_mask;
};
/**
@@ -402,6 +404,7 @@ EXPORT_SYMBOL(miic_destroy);
static int miic_init_hw(struct miic *miic, u32 cfg_mode)
{
+ u8 sw_mode_mask = miic->of_data->sw_mode_mask;
int port;
/* Unlock write access to accessory registers (cf datasheet). If this
@@ -414,7 +417,7 @@ static int miic_init_hw(struct miic *miic, u32 cfg_mode)
miic_reg_writel(miic, MIIC_PRCMD, 0x0001);
miic_reg_writel(miic, MIIC_MODCTRL,
- FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode));
+ ((cfg_mode << __ffs(sw_mode_mask)) & sw_mode_mask));
for (port = 0; port < miic->of_data->miic_port_max; port++) {
miic_converter_enable(miic, port, 0);
@@ -580,6 +583,7 @@ static struct miic_of_data rzn1_miic_of_data = {
.index_to_string_count = ARRAY_SIZE(index_to_string),
.miic_port_start = 1,
.miic_port_max = 5,
+ .sw_mode_mask = GENMASK(4, 0),
};
static const struct of_device_id miic_of_mtable[] = {
--
2.51.0On Thu, Sep 04, 2025 at 12:42:00PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Move the hardcoded switch mode mask definition into the SoC-specific
> miic_of_data structure. This allows each SoC to define its own mask
> value rather than relying on a single fixed constant. For RZ/N1 the
> mask remains GENMASK(4, 0).
>
> This is in preparation for adding support for RZ/T2H, where the
> switch mode mask is GENMASK(2, 0).
> -#define MIIC_MODCTRL_SW_MODE GENMASK(4, 0)
> miic_reg_writel(miic, MIIC_MODCTRL,
> - FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode));
> + ((cfg_mode << __ffs(sw_mode_mask)) & sw_mode_mask));
_ffs() should return 0 for both GENMASK(2,0) and GENMASK(4, 0). So
this __ffs() is pointless.
You might however want to add a comment that this assumption is being
made.
Andrew
---
pw-bot: cr
Hi Andrew and Geert, Thank you for the review. On Thu, Sep 4, 2025 at 9:37 PM Andrew Lunn <andrew@lunn.ch> wrote: > > On Thu, Sep 04, 2025 at 12:42:00PM +0100, Prabhakar wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Move the hardcoded switch mode mask definition into the SoC-specific > > miic_of_data structure. This allows each SoC to define its own mask > > value rather than relying on a single fixed constant. For RZ/N1 the > > mask remains GENMASK(4, 0). > > > > This is in preparation for adding support for RZ/T2H, where the > > switch mode mask is GENMASK(2, 0). > > > -#define MIIC_MODCTRL_SW_MODE GENMASK(4, 0) > > > miic_reg_writel(miic, MIIC_MODCTRL, > > - FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode)); > > + ((cfg_mode << __ffs(sw_mode_mask)) & sw_mode_mask)); > > _ffs() should return 0 for both GENMASK(2,0) and GENMASK(4, 0). So > this __ffs() is pointless. > Agreed. > You might however want to add a comment that this assumption is being > made. > I will add the below comment for this, so that once Geert's series [0] hits in it can be easily searched and replaced. /* * TODO: Replace with FIELD_PREP() when compile-time * constant restriction is lifted. Currently __ffs() returns 0 for sw_mode_mask. */ [0] https://lore.kernel.org/all/cover.1739540679.git.geert+renesas@glider.be Cheers, Prabhakar
Hi Andrew,
On Thu, 4 Sept 2025 at 22:37, Andrew Lunn <andrew@lunn.ch> wrote:
> On Thu, Sep 04, 2025 at 12:42:00PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Move the hardcoded switch mode mask definition into the SoC-specific
> > miic_of_data structure. This allows each SoC to define its own mask
> > value rather than relying on a single fixed constant. For RZ/N1 the
> > mask remains GENMASK(4, 0).
> >
> > This is in preparation for adding support for RZ/T2H, where the
> > switch mode mask is GENMASK(2, 0).
>
> > -#define MIIC_MODCTRL_SW_MODE GENMASK(4, 0)
>
> > miic_reg_writel(miic, MIIC_MODCTRL,
> > - FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode));
> > + ((cfg_mode << __ffs(sw_mode_mask)) & sw_mode_mask));
>
> _ffs() should return 0 for both GENMASK(2,0) and GENMASK(4, 0). So
> this __ffs() is pointless.
>
> You might however want to add a comment that this assumption is being
> made.
I guess Prabhakar did it this way to make it easier to find
candidates for a future conversion to field_prep(), if this ever becomes
available[1].
[1] "[PATCH v3 0/4] Non-const bitfield helpers"
https://lore.kernel.org/all/cover.1739540679.git.geert+renesas@glider.be
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert, On Fri, Sep 5, 2025 at 8:02 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Andrew, > > On Thu, 4 Sept 2025 at 22:37, Andrew Lunn <andrew@lunn.ch> wrote: > > On Thu, Sep 04, 2025 at 12:42:00PM +0100, Prabhakar wrote: > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > Move the hardcoded switch mode mask definition into the SoC-specific > > > miic_of_data structure. This allows each SoC to define its own mask > > > value rather than relying on a single fixed constant. For RZ/N1 the > > > mask remains GENMASK(4, 0). > > > > > > This is in preparation for adding support for RZ/T2H, where the > > > switch mode mask is GENMASK(2, 0). > > > > > -#define MIIC_MODCTRL_SW_MODE GENMASK(4, 0) > > > > > miic_reg_writel(miic, MIIC_MODCTRL, > > > - FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode)); > > > + ((cfg_mode << __ffs(sw_mode_mask)) & sw_mode_mask)); > > > > _ffs() should return 0 for both GENMASK(2,0) and GENMASK(4, 0). So > > this __ffs() is pointless. > > > > You might however want to add a comment that this assumption is being > > made. > > I guess Prabhakar did it this way to make it easier to find > candidates for a future conversion to field_prep(), if this ever becomes > available[1]. > > [1] "[PATCH v3 0/4] Non-const bitfield helpers" > https://lore.kernel.org/all/cover.1739540679.git.geert+renesas@glider.be > Ah thanks, I wanted to explore this and add a new macro but I thought it might delay this series so I dropped it. Hopefully your series will get in soon. Cheers, Prabhakar
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