This series adds add equalization settings for 8.0 GT/s and 32.0 GT/s,
and add PCIe lane equalization preset properties for 8.0 GT/s and
16.0 GT/s for sa8775p ride platform, which fix AER errors.

While equalization settings for 16 GT/s have already been set, this
update adds the required equalization settings for PCIe operating at
8.0 GT/s and 32.0 GT/s, including the configuration of shadow registers,
ensuring optimal performance and stability.

The DT change for sa8775p add PCIe lane equalization preset properties
for 8 GT/s and 16 GT/s data rates used in lane equalization procedure.

Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>

Changes in v6:
- Add Fix tag and format as Xmax order (Mani)
- Delte the blank line (Neil)
- Link to v5: https://lore.kernel.org/all/20250819071649.1531437-1-ziyue.zhang@oss.qualcomm.com/

Changes in v5:
- Add support for 32.0 GT/s
- Add warning print for speed higher than 32.0 GT/s (Mani)
- Link to v4: https://lore.kernel.org/all/20250714082110.3890821-1-ziyue.zhang@oss.qualcomm.com/

Changes in v4:
- Bail out early if the link speed > 16 GT/s and use pci->max_link_speed directly (Mani)
- Fix the build warning. (Bjorn)
- Link to v3: https://lore.kernel.org/all/8ccd3731-8dbc-4972-a79a-ba78e90ec4a8@quicinc.com/

Changes in v3:
- Delte TODO tag and warn print in pcie-qcom-common.c. (Bjorn)
- Refined the commit message for better readability. (Bjorn)
- Link to v2: https://lore.kernel.org/all/20250611100319.464803-1-quic_ziyuzhan@quicinc.com/

Changes in v2:
- Update code in pcie-qcom-common.c make it easier to read. (Neil)
- Fix the compile error.
- Link to v1: https://lore.kernel.org/all/20250604091946.1890602-1-quic_ziyuzhan@quicinc.com


Ziyue Zhang (3):
  PCI: qcom: Add equalization settings for 8.0 GT/s and 32.0 GT/s
  PCI: qcom: fix macro typo for CURSOR
  arm64: dts: qcom: lemans: Add PCIe lane equalization preset properties

 arch/arm64/boot/dts/qcom/lemans.dtsi          |  6 ++
 drivers/pci/controller/dwc/pcie-designware.h  |  5 +-
 drivers/pci/controller/dwc/pcie-qcom-common.c | 58 +++++++++++--------
 drivers/pci/controller/dwc/pcie-qcom-common.h |  2 +-
 drivers/pci/controller/dwc/pcie-qcom-ep.c     |  6 +-
 drivers/pci/controller/dwc/pcie-qcom.c        |  6 +-
 6 files changed, 49 insertions(+), 34 deletions(-)


base-commit: 3ac864c2d9bb8608ee236e89bf561811613abfce
-- 
2.43.0

On Thu, 04 Sep 2025 14:52:22 +0800, Ziyue Zhang wrote:
> This series adds add equalization settings for 8.0 GT/s and 32.0 GT/s,
> and add PCIe lane equalization preset properties for 8.0 GT/s and
> 16.0 GT/s for sa8775p ride platform, which fix AER errors.
> 
> While equalization settings for 16 GT/s have already been set, this
> update adds the required equalization settings for PCIe operating at
> 8.0 GT/s and 32.0 GT/s, including the configuration of shadow registers,
> ensuring optimal performance and stability.
> 
> [...]

Applied, thanks!

[3/3] arm64: dts: qcom: lemans: Add PCIe lane equalization preset properties
      commit: b4f745f1d8adad62ba8c2065873c8a857ed4c3da

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>

On Thu, 04 Sep 2025 14:52:22 +0800, Ziyue Zhang wrote:
> This series adds add equalization settings for 8.0 GT/s and 32.0 GT/s,
> and add PCIe lane equalization preset properties for 8.0 GT/s and
> 16.0 GT/s for sa8775p ride platform, which fix AER errors.
> 
> While equalization settings for 16 GT/s have already been set, this
> update adds the required equalization settings for PCIe operating at
> 8.0 GT/s and 32.0 GT/s, including the configuration of shadow registers,
> ensuring optimal performance and stability.
> 
> [...]

Applied, thanks!

[1/3] PCI: qcom: Add equalization settings for 8.0 GT/s and 32.0 GT/s
      commit: 37bf0f4e39de9b53bc6f8d3702b021e2c6b5bae3
[2/3] PCI: qcom: fix macro typo for CURSOR
      commit: ea5fbbc15906abdef174c88cecfec4b2a0c748b9

Best regards,
-- 
Manivannan Sadhasivam <mani@kernel.org>