Serial engines 2 and 3 on the IPQ5424 support I2C. The I2C instance
operates on serial engine 2, designated as i2c0, and on serial engine 3,
designated as i2c1. Add both the i2c0 and i2c1 nodes.
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
---
v2: Remove assigned-clock and add opp table to configure the frequency of se clock
arch/arm64/boot/dts/qcom/ipq5424.dtsi | 28 +++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
index 67877fbbdf3a..0d8ea9a8c600 100644
--- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
@@ -173,6 +173,14 @@ memory@80000000 {
reg = <0x0 0x80000000 0x0 0x0>;
};
+ i2c_opp_table_64mhz: opp-table-qup64mhz {
+ compatible = "operating-points-v2";
+
+ opp-64000000 {
+ opp-hz = /bits/ 64 <64000000>;
+ };
+ };
+
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
@@ -519,6 +527,26 @@ uart1: serial@1a84000 {
interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
};
+ i2c0: i2c@1a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x01a88000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_I2C0_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
+ operating-points-v2 = <&i2c_opp_table_64mhz>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@1a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x01a8c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_I2C1_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
+ operating-points-v2 = <&i2c_opp_table_64mhz>;
+ status = "disabled";
+ };
+
spi0: spi@1a90000 {
compatible = "qcom,geni-spi";
reg = <0 0x01a90000 0 0x4000>;
--
2.34.1