drivers/soc/tegra/fuse/speedo-tegra210.c | 62 ++++++++++++++++++++++---------- 1 file changed, 43 insertions(+), 19 deletions(-)
From: Aaron Kling <webgeek1234@gmail.com>
Existing code only sets cpu and gpu speedo ids 0 and 1. The cpu dvfs
code supports 11 ids and nouveau supports 5. This aligns with what the
downstream vendor kernel supports. Align skus with the downstream list.
The Tegra210 CVB tables were added in the first referenced fixes commit.
Since then, all Tegra210 socs have tried to scale to 1.9 GHz, when the
supported devkits are only supposed to scale to 1.5 or 1.7 GHZ.
Overclocking should not be the default state.
Fixes: 2b2dbc2f94e5 ("clk: tegra: dfll: add CVB tables for Tegra210")
Fixes: 579db6e5d9b8 ("arm64: tegra: Enable DFLL support on Jetson Nano")
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
The Tegra210 CVB tables were added in commit 2b2dbc2f94e5. Since then,
all Tegra210 socs have tried to scale the cpu to 1.9 GHz, when the
supported devkits are only supposed to scale to 1.5 or 1.7 GHZ.
Overclocking should not be the default state.
---
Changes in v3:
- Drop all patches related to limiting cpu frequency from a dt property
- Link to v2: https://lore.kernel.org/r/20250903-tegra210-speedo-v2-0-89e6f86b8942@gmail.com
Changes in v2:
- Define units in patch 1
- Update patch 1 commit message to better explain the need
- Pull all downstream sku's into patch 2, which eliminates patch 3
- Update patch 4 commit message to indicate the limit is due to thermal
constraints.
- Link to v1: https://lore.kernel.org/r/20250816-tegra210-speedo-v1-0-a981360adc27@gmail.com
---
drivers/soc/tegra/fuse/speedo-tegra210.c | 62 ++++++++++++++++++++++----------
1 file changed, 43 insertions(+), 19 deletions(-)
diff --git a/drivers/soc/tegra/fuse/speedo-tegra210.c b/drivers/soc/tegra/fuse/speedo-tegra210.c
index 695d0b7f9a8abe53c497155603147420cda40b63..60356159e00d2059e55eaacba27b5ca63bf96c90 100644
--- a/drivers/soc/tegra/fuse/speedo-tegra210.c
+++ b/drivers/soc/tegra/fuse/speedo-tegra210.c
@@ -65,27 +65,51 @@ static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info,
sku_info->gpu_speedo_id = 0;
*threshold = THRESHOLD_INDEX_0;
- switch (sku) {
- case 0x00: /* Engineering SKU */
- case 0x01: /* Engineering SKU */
- case 0x07:
- case 0x17:
- case 0x27:
- if (speedo_rev >= 2)
+ if (speedo_rev >= 2) {
+ switch (sku) {
+ case 0x00: /* Engineering SKU */
+ case 0x01: /* Engineering SKU */
+ case 0x13:
+ sku_info->cpu_speedo_id = 5;
+ sku_info->gpu_speedo_id = 2;
+ break;
+
+ case 0x07:
+ case 0x17:
+ case 0x1F:
+ sku_info->cpu_speedo_id = 7;
+ sku_info->gpu_speedo_id = 2;
+ break;
+
+ case 0x27:
+ sku_info->cpu_speedo_id = 1;
+ sku_info->gpu_speedo_id = 2;
+ break;
+
+ case 0x83:
+ sku_info->cpu_speedo_id = 3;
+ sku_info->gpu_speedo_id = 3;
+ break;
+
+ case 0x87:
+ sku_info->cpu_speedo_id = 2;
sku_info->gpu_speedo_id = 1;
- break;
-
- case 0x13:
- if (speedo_rev >= 2)
- sku_info->gpu_speedo_id = 1;
-
- sku_info->cpu_speedo_id = 1;
- break;
-
- default:
+ break;
+
+ case 0x8F:
+ sku_info->cpu_speedo_id = 9;
+ sku_info->gpu_speedo_id = 2;
+ break;
+
+ default:
+ pr_err("Tegra210: unknown revision 2 or newer SKU %#04x\n", sku);
+ /* Using the default for the error case */
+ break;
+ }
+ } else if (sku == 0x00 || sku == 0x01 || sku == 0x07 || sku == 0x13 || sku == 0x17) {
+ sku_info->gpu_speedo_id = 1;
+ } else {
pr_err("Tegra210: unknown SKU %#04x\n", sku);
- /* Using the default for the error case */
- break;
}
}
---
base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585
change-id: 20250812-tegra210-speedo-470691e8b8cc
Best regards,
--
Aaron Kling <webgeek1234@gmail.com>On 04/09/2025 02:58, Aaron Kling via B4 Relay wrote: > From: Aaron Kling <webgeek1234@gmail.com> > > Existing code only sets cpu and gpu speedo ids 0 and 1. The cpu dvfs > code supports 11 ids and nouveau supports 5. This aligns with what the > downstream vendor kernel supports. Align skus with the downstream list. Do you have a reference for the downstream kernel change you are referring to? I have found this change [0]. However, this does not quite align with what you have in this patch. Jon [0] https://nv-tegra.nvidia.com/r/plugins/gitiles/linux-5.10/+/2a8660e3d1e4f75ba4390b72991744174237b025%5E%21/#F0 -- nvpublic
On Thu, Sep 18, 2025 at 4:45 AM Jon Hunter <jonathanh@nvidia.com> wrote: > > > On 04/09/2025 02:58, Aaron Kling via B4 Relay wrote: > > From: Aaron Kling <webgeek1234@gmail.com> > > > > Existing code only sets cpu and gpu speedo ids 0 and 1. The cpu dvfs > > code supports 11 ids and nouveau supports 5. This aligns with what the > > downstream vendor kernel supports. Align skus with the downstream list. > > Do you have a reference for the downstream kernel change you are > referring to? I have found this change [0]. However, this does not quite > align with what you have in this patch. This is based on L4T r32.7.6 [0], which builds up the list over several commits, so I can't link to just one. The first revision only added sku's that I had specifically verified. Mikko suggested to just import everything from downstream and to simplify the conditionals. And that's this revision. > > Jon > > [0] > https://nv-tegra.nvidia.com/r/plugins/gitiles/linux-5.10/+/2a8660e3d1e4f75ba4390b72991744174237b025%5E%21/#F0 > > -- > nvpublic > Aaron [0] https://nv-tegra.nvidia.com/r/plugins/gitiles/linux-4.9/+/refs/tags/tegra-l4t-r32.7.6_good/drivers/soc/tegra/fuse/speedo-tegra210.c#72
On 18/09/2025 18:19, Aaron Kling wrote: > On Thu, Sep 18, 2025 at 4:45 AM Jon Hunter <jonathanh@nvidia.com> wrote: >> >> >> On 04/09/2025 02:58, Aaron Kling via B4 Relay wrote: >>> From: Aaron Kling <webgeek1234@gmail.com> >>> >>> Existing code only sets cpu and gpu speedo ids 0 and 1. The cpu dvfs >>> code supports 11 ids and nouveau supports 5. This aligns with what the >>> downstream vendor kernel supports. Align skus with the downstream list. >> >> Do you have a reference for the downstream kernel change you are >> referring to? I have found this change [0]. However, this does not quite >> align with what you have in this patch. > > This is based on L4T r32.7.6 [0], which builds up the list over > several commits, so I can't link to just one. The first revision only > added sku's that I had specifically verified. Mikko suggested to just > import everything from downstream and to simplify the conditionals. > And that's this revision. ... > [0] https://nv-tegra.nvidia.com/r/plugins/gitiles/linux-4.9/+/refs/tags/tegra-l4t-r32.7.6_good/drivers/soc/tegra/fuse/speedo-tegra210.c#72 Thanks! I saw Mikko's comments on V2 and that makes sense. The problem I have is that comparing this with the above, it is not clear that these are equivalent. The above is using the 'a02' chip version for setting the speedo IDs but this is using the speedo revision. Now it might turn out this is equivalent, but it is not obvious to me. Ideally we would end up with something similar to the above. Jon -- nvpublic
On Fri, Sep 19, 2025 at 4:55 AM Jon Hunter <jonathanh@nvidia.com> wrote: > > > On 18/09/2025 18:19, Aaron Kling wrote: > > On Thu, Sep 18, 2025 at 4:45 AM Jon Hunter <jonathanh@nvidia.com> wrote: > >> > >> > >> On 04/09/2025 02:58, Aaron Kling via B4 Relay wrote: > >>> From: Aaron Kling <webgeek1234@gmail.com> > >>> > >>> Existing code only sets cpu and gpu speedo ids 0 and 1. The cpu dvfs > >>> code supports 11 ids and nouveau supports 5. This aligns with what the > >>> downstream vendor kernel supports. Align skus with the downstream list. > >> > >> Do you have a reference for the downstream kernel change you are > >> referring to? I have found this change [0]. However, this does not quite > >> align with what you have in this patch. > > > > This is based on L4T r32.7.6 [0], which builds up the list over > > several commits, so I can't link to just one. The first revision only > > added sku's that I had specifically verified. Mikko suggested to just > > import everything from downstream and to simplify the conditionals. > > And that's this revision. > > ... > > > [0] https://nv-tegra.nvidia.com/r/plugins/gitiles/linux-4.9/+/refs/tags/tegra-l4t-r32.7.6_good/drivers/soc/tegra/fuse/speedo-tegra210.c#72 > > > Thanks! I saw Mikko's comments on V2 and that makes sense. The problem I > have is that comparing this with the above, it is not clear that these > are equivalent. The above is using the 'a02' chip version for setting > the speedo IDs but this is using the speedo revision. Now it might turn > out this is equivalent, but it is not obvious to me. Ideally we would > end up with something similar to the above. Thanks for noticing this discrepancy. I will fix and verify, then send a new revision. Aaron
On Thursday, September 4, 2025 10:58 AM Aaron Kling via B4 Relay wrote:
> From: Aaron Kling <webgeek1234@gmail.com>
>
> Existing code only sets cpu and gpu speedo ids 0 and 1. The cpu dvfs
> code supports 11 ids and nouveau supports 5. This aligns with what the
> downstream vendor kernel supports. Align skus with the downstream list.
>
> The Tegra210 CVB tables were added in the first referenced fixes commit.
> Since then, all Tegra210 socs have tried to scale to 1.9 GHz, when the
> supported devkits are only supposed to scale to 1.5 or 1.7 GHZ.
> Overclocking should not be the default state.
>
> Fixes: 2b2dbc2f94e5 ("clk: tegra: dfll: add CVB tables for Tegra210")
> Fixes: 579db6e5d9b8 ("arm64: tegra: Enable DFLL support on Jetson Nano")
> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> ---
> The Tegra210 CVB tables were added in commit 2b2dbc2f94e5. Since then,
> all Tegra210 socs have tried to scale the cpu to 1.9 GHz, when the
> supported devkits are only supposed to scale to 1.5 or 1.7 GHZ.
> Overclocking should not be the default state.
> ---
> Changes in v3:
> - Drop all patches related to limiting cpu frequency from a dt property
> - Link to v2: https://lore.kernel.org/r/20250903-tegra210-speedo-v2-0-89e6f86b8942@gmail.com
>
> Changes in v2:
> - Define units in patch 1
> - Update patch 1 commit message to better explain the need
> - Pull all downstream sku's into patch 2, which eliminates patch 3
> - Update patch 4 commit message to indicate the limit is due to thermal
> constraints.
> - Link to v1: https://lore.kernel.org/r/20250816-tegra210-speedo-v1-0-a981360adc27@gmail.com
> ---
> drivers/soc/tegra/fuse/speedo-tegra210.c | 62 ++++++++++++++++++++++----------
> 1 file changed, 43 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/soc/tegra/fuse/speedo-tegra210.c b/drivers/soc/tegra/fuse/speedo-tegra210.c
> index 695d0b7f9a8abe53c497155603147420cda40b63..60356159e00d2059e55eaacba27b5ca63bf96c90 100644
> --- a/drivers/soc/tegra/fuse/speedo-tegra210.c
> +++ b/drivers/soc/tegra/fuse/speedo-tegra210.c
> @@ -65,27 +65,51 @@ static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info,
> sku_info->gpu_speedo_id = 0;
> *threshold = THRESHOLD_INDEX_0;
>
> - switch (sku) {
> - case 0x00: /* Engineering SKU */
> - case 0x01: /* Engineering SKU */
> - case 0x07:
> - case 0x17:
> - case 0x27:
> - if (speedo_rev >= 2)
> + if (speedo_rev >= 2) {
> + switch (sku) {
> + case 0x00: /* Engineering SKU */
> + case 0x01: /* Engineering SKU */
> + case 0x13:
> + sku_info->cpu_speedo_id = 5;
> + sku_info->gpu_speedo_id = 2;
> + break;
> +
> + case 0x07:
> + case 0x17:
> + case 0x1F:
> + sku_info->cpu_speedo_id = 7;
> + sku_info->gpu_speedo_id = 2;
> + break;
> +
> + case 0x27:
> + sku_info->cpu_speedo_id = 1;
> + sku_info->gpu_speedo_id = 2;
> + break;
> +
> + case 0x83:
> + sku_info->cpu_speedo_id = 3;
> + sku_info->gpu_speedo_id = 3;
> + break;
> +
> + case 0x87:
> + sku_info->cpu_speedo_id = 2;
> sku_info->gpu_speedo_id = 1;
> - break;
> -
> - case 0x13:
> - if (speedo_rev >= 2)
> - sku_info->gpu_speedo_id = 1;
> -
> - sku_info->cpu_speedo_id = 1;
> - break;
> -
> - default:
> + break;
> +
> + case 0x8F:
> + sku_info->cpu_speedo_id = 9;
> + sku_info->gpu_speedo_id = 2;
> + break;
> +
> + default:
> + pr_err("Tegra210: unknown revision 2 or newer SKU %#04x\n", sku);
> + /* Using the default for the error case */
> + break;
> + }
> + } else if (sku == 0x00 || sku == 0x01 || sku == 0x07 || sku == 0x13 || sku == 0x17) {
> + sku_info->gpu_speedo_id = 1;
> + } else {
> pr_err("Tegra210: unknown SKU %#04x\n", sku);
> - /* Using the default for the error case */
> - break;
> }
> }
>
>
> ---
> base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585
> change-id: 20250812-tegra210-speedo-470691e8b8cc
>
> Best regards,
>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
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