From: Aaron Kling <webgeek1234@gmail.com>

These are needed for dynamic frequency scaling of the EMC controller.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
 .../bindings/memory-controllers/nvidia,tegra210-emc.yaml    | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
index bc8477e7ab193b7880bb681037985f3fccebf02f..6cc1c7fc7a328bd18c7c0beb535c1ff918bcdb2a 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
@@ -33,6 +33,9 @@ properties:
     items:
       - description: EMC general interrupt
 
+  "#interconnect-cells":
+    const: 0
+
   memory-region:
     maxItems: 1
     description:
@@ -44,12 +47,19 @@ properties:
     description:
       phandle of the memory controller node
 
+  operating-points-v2:
+    description:
+      Should contain freqs and voltages and opp-supported-hw property, which
+      is a bitfield indicating SoC speedo ID mask.
+
 required:
   - compatible
   - reg
   - clocks
   - clock-names
+  - "#interconnect-cells"
   - nvidia,memory-controller
+  - operating-points-v2
 
 additionalProperties: false
 
@@ -79,4 +89,7 @@ examples:
         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
         memory-region = <&emc_table>;
         nvidia,memory-controller = <&mc>;
+        operating-points-v2 = <&dvfs_opp_table>;
+
+        #interconnect-cells = <0>;
     };

-- 
2.50.1

On Wed, Sep 03, 2025 at 02:50:09PM -0500, Aaron Kling wrote:
> These are needed for dynamic frequency scaling of the EMC controller.
> 
> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> ---
>  .../bindings/memory-controllers/nvidia,tegra210-emc.yaml    | 13 +++++++++++++
>  1 file changed, 13 insertions(+)

I asked to order patches within patchset in some logical way. First
patch was memory, second other, third again memory.

There are no dependencies explained, so this looks like groupping
unrelated patches, therefore SPLIT finally the patchset per subsystem.

> 
> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
> index bc8477e7ab193b7880bb681037985f3fccebf02f..6cc1c7fc7a328bd18c7c0beb535c1ff918bcdb2a 100644
> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
> @@ -33,6 +33,9 @@ properties:
>      items:
>        - description: EMC general interrupt
>  
> +  "#interconnect-cells":
> +    const: 0
> +
>    memory-region:
>      maxItems: 1
>      description:
> @@ -44,12 +47,19 @@ properties:
>      description:
>        phandle of the memory controller node
>  
> +  operating-points-v2:
> +    description:
> +      Should contain freqs and voltages and opp-supported-hw property, which
> +      is a bitfield indicating SoC speedo ID mask.
> +

No opp-table?

>  required:
>    - compatible
>    - reg
>    - clocks
>    - clock-names
> +  - "#interconnect-cells"

That's ABI break without explanation.

>    - nvidia,memory-controller
> +  - operating-points-v2

Best regards,
Krzysztof

On Thu, Sep 4, 2025 at 3:11 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On Wed, Sep 03, 2025 at 02:50:09PM -0500, Aaron Kling wrote:
> > These are needed for dynamic frequency scaling of the EMC controller.
> >
> > Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> > ---
> >  .../bindings/memory-controllers/nvidia,tegra210-emc.yaml    | 13 +++++++++++++
> >  1 file changed, 13 insertions(+)
>
> I asked to order patches within patchset in some logical way. First
> patch was memory, second other, third again memory.
>
> There are no dependencies explained, so this looks like groupping
> unrelated patches, therefore SPLIT finally the patchset per subsystem.
>
> >
> > diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
> > index bc8477e7ab193b7880bb681037985f3fccebf02f..6cc1c7fc7a328bd18c7c0beb535c1ff918bcdb2a 100644
> > --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
> > +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
> > @@ -33,6 +33,9 @@ properties:
> >      items:
> >        - description: EMC general interrupt
> >
> > +  "#interconnect-cells":
> > +    const: 0
> > +
> >    memory-region:
> >      maxItems: 1
> >      description:
> > @@ -44,12 +47,19 @@ properties:
> >      description:
> >        phandle of the memory controller node
> >
> > +  operating-points-v2:
> > +    description:
> > +      Should contain freqs and voltages and opp-supported-hw property, which
> > +      is a bitfield indicating SoC speedo ID mask.
> > +
>
> No opp-table?

All other tegra devices have the opp tables in standalone nodes, not
as subnodes to their users. I followed that style here, see patch 8.

Aaron