Add bindings for pin controller in SDM660 Low Power Audio SubSystem
(LPASS).

Co-developed-by: Richard Acayan <mailingradian@gmail.com>
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Signed-off-by: Nickolay Goppen <setotau@mainlining.org>
---
 .../pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml     | 109 +++++++++++++++++++++
 1 file changed, 109 insertions(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..175d5dbf54fa3669805cb69d5b4df19ab57c1520
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml
@@ -0,0 +1,109 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SDM660 SoC LPASS LPI TLMM
+
+maintainers:
+  - Nickolay Goppen <setotau@mainlining.org>
+
+description:
+  Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
+  (LPASS) Low Power Island (LPI) of Qualcomm SDM660 SoC.
+
+properties:
+  compatible:
+    const: qcom,sdm660-lpass-lpi-pinctrl
+
+  reg:
+    items:
+      - description: LPASS LPI TLMM Control and Status registers
+
+patternProperties:
+  "-state$":
+    oneOf:
+      - $ref: "#/$defs/qcom-sdm660-lpass-state"
+      - patternProperties:
+          "-pins$":
+            $ref: "#/$defs/qcom-sdm660-lpass-state"
+        additionalProperties: false
+
+$defs:
+  qcom-sdm660-lpass-state:
+    type: object
+    description:
+      Pinctrl node's client devices use subnodes for desired pin configuration.
+      Client device subnodes use below standard properties.
+    $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
+    unevaluatedProperties: false
+
+    properties:
+      pins:
+        description:
+          List of gpio pins affected by the properties specified in this
+          subnode.
+        items:
+          pattern: "^gpio([0-9]|[1-2][0-9]|3[0-1])$"
+
+      function:
+        enum: [ gpio, comp_rx, dmic1_clk, dmic1_data, dmic2_clk, dmic2_data,
+                mclk0, pdm_tx, pdm_clk, pdm_rx, pdm_sync ]
+        description:
+          Specify the alternative function to be configured for the specified
+          pins.
+
+allOf:
+  - $ref: qcom,lpass-lpi-common.yaml#
+
+required:
+  - compatible
+  - reg
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    lpi_tlmm: pinctrl@15070000 {
+        compatible = "qcom,sdm660-lpass-lpi-pinctrl";
+        reg = <0x15070000 0x20000>;
+        gpio-controller;
+        #gpio-cells = <2>;
+        gpio-ranges = <&lpi_tlmm 0 0 32>;
+
+        cdc_pdm_default: cdc-pdm-default-state {
+                clk-pins {
+                    pins = "gpio18";
+                    function = "pdm_clk";
+                    drive-strength = <8>;
+                    output-high;
+                };
+
+                sync-pins{
+                    pins = "gpio19";
+                    function = "pdm_sync";
+                    drive-strength = <4>;
+                    output-high;
+                };
+
+                tx-pins {
+                    pins = "gpio20";
+                    function = "pdm_tx";
+                    drive-strength = <8>;
+                };
+
+                rx-pins {
+                    pins = "gpio21", "gpio23", "gpio25";
+                    function = "pdm_rx";
+                    drive-strength = <4>;
+                    output-high;
+                };
+        };
+
+        cdc_comp_default: cdc-comp-default-state {
+                pins = "gpio22", "gpio24";
+                function = "comp_rx";
+                drive-strength = <8>;
+        };
+    };

-- 
2.51.0

On 03/09/2025 15:39, Nickolay Goppen wrote:
> +
> +examples:
> +  - |
> +    lpi_tlmm: pinctrl@15070000 {
> +        compatible = "qcom,sdm660-lpass-lpi-pinctrl";
> +        reg = <0x15070000 0x20000>;
> +        gpio-controller;
> +        #gpio-cells = <2>;
> +        gpio-ranges = <&lpi_tlmm 0 0 32>;
> +
> +        cdc_pdm_default: cdc-pdm-default-state {
> +                clk-pins {

Messed indentation. Keep four spaces.

> +                    pins = "gpio18";
> +                    function = "pdm_clk";
> +                    drive-strength = <8>;
> +                    output-high;
> +                };
> +
> +                sync-pins{
> +                    pins = "gpio19";
> +                    function = "pdm_sync";
> +                    drive-strength = <4>;
> +                    output-high;
> +                };
> +
> +                tx-pins {
> +                    pins = "gpio20";
> +                    function = "pdm_tx";
> +                    drive-strength = <8>;
> +                };
> +
> +                rx-pins {
> +                    pins = "gpio21", "gpio23", "gpio25";
> +                    function = "pdm_rx";
> +                    drive-strength = <4>;
> +                    output-high;
> +                };
> +        };
> +
> +        cdc_comp_default: cdc-comp-default-state {
> +                pins = "gpio22", "gpio24";

Also here.

With these fixed:

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof