On X Elite platform, the eDP PHY uses one more clock called
refclk. Add it to the schema.
Cc: stable@vger.kernel.org # v6.10
Fixes: 5d5607861350 ("dt-bindings: phy: qcom-edp: Add X1E80100 PHY compatibles")
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
.../devicetree/bindings/phy/qcom,edp-phy.yaml | 28 +++++++++++++++++++++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
index eb97181cbb9579893b4ee26a39c3559ad87b2fba..a8ba0aa9ff9d83f317bd897a7d564f7e13f6a1e2 100644
--- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
@@ -37,12 +37,15 @@ properties:
- description: PLL register block
clocks:
- maxItems: 2
+ minItems: 2
+ maxItems: 3
clock-names:
+ minItems: 2
items:
- const: aux
- const: cfg_ahb
+ - const: refclk
"#clock-cells":
const: 1
@@ -64,6 +67,29 @@ required:
- "#clock-cells"
- "#phy-cells"
+allOf:
+ - if:
+ properties:
+ compatible:
+ enum:
+ - qcom,x1e80100-dp-phy
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 3
+ clock-names:
+ minItems: 3
+ maxItems: 3
+ else:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ minItems: 2
+ maxItems: 2
+
additionalProperties: false
examples:
--
2.45.2
On 03/09/2025 14:37, Abel Vesa wrote: > On X Elite platform, the eDP PHY uses one more clock called > refclk. Add it to the schema. > > Cc: stable@vger.kernel.org # v6.10 > Fixes: 5d5607861350 ("dt-bindings: phy: qcom-edp: Add X1E80100 PHY compatibles") > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > .../devicetree/bindings/phy/qcom,edp-phy.yaml | 28 +++++++++++++++++++++- > 1 file changed, 27 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml > index eb97181cbb9579893b4ee26a39c3559ad87b2fba..a8ba0aa9ff9d83f317bd897a7d564f7e13f6a1e2 100644 > --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml > +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml > @@ -37,12 +37,15 @@ properties: > - description: PLL register block > > clocks: > - maxItems: 2 > + minItems: 2 > + maxItems: 3 > > clock-names: > + minItems: 2 > items: > - const: aux > - const: cfg_ahb > + - const: refclk Name is: "ref" > > "#clock-cells": > const: 1 > @@ -64,6 +67,29 @@ required: > - "#clock-cells" > - "#phy-cells" > > +allOf: > + - if: > + properties: > + compatible: > + enum: > + - qcom,x1e80100-dp-phy > + then: > + properties: > + clocks: > + minItems: 3 That's an ABI break, so you need to explain it and mention the impact. Reason that there is one more clock, but everything was working fine, is not usually enough. Best regards, Krzysztof
On 04/09/2025 08:50, Krzysztof Kozlowski wrote: >> +allOf: >> + - if: >> + properties: >> + compatible: >> + enum: >> + - qcom,x1e80100-dp-phy >> + then: >> + properties: >> + clocks: >> + minItems: 3 > > That's an ABI break, so you need to explain it and mention the impact. > Reason that there is one more clock, but everything was working fine, is > not usually enough. Heh, I already asked for that at v1 and nothing improved. Best regards, Krzysztof
On 25-09-04 08:51:49, Krzysztof Kozlowski wrote: > On 04/09/2025 08:50, Krzysztof Kozlowski wrote: > >> +allOf: > >> + - if: > >> + properties: > >> + compatible: > >> + enum: > >> + - qcom,x1e80100-dp-phy > >> + then: > >> + properties: > >> + clocks: > >> + minItems: 3 > > > > That's an ABI break, so you need to explain it and mention the impact. > > Reason that there is one more clock, but everything was working fine, is > > not usually enough. > Heh, I already asked for that at v1 and nothing improved. I missed that comment. Sorry about that. Will address in v3. Thanks for reviewing.
On 9/3/25 2:37 PM, Abel Vesa wrote: > On X Elite platform, the eDP PHY uses one more clock called > refclk. Add it to the schema. > > Cc: stable@vger.kernel.org # v6.10 > Fixes: 5d5607861350 ("dt-bindings: phy: qcom-edp: Add X1E80100 PHY compatibles") > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > .../devicetree/bindings/phy/qcom,edp-phy.yaml | 28 +++++++++++++++++++++- > 1 file changed, 27 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml > index eb97181cbb9579893b4ee26a39c3559ad87b2fba..a8ba0aa9ff9d83f317bd897a7d564f7e13f6a1e2 100644 > --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml > +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml > @@ -37,12 +37,15 @@ properties: > - description: PLL register block > > clocks: > - maxItems: 2 > + minItems: 2 > + maxItems: 3 > > clock-names: > + minItems: 2 > items: > - const: aux > - const: cfg_ahb > + - const: refclk "ref"? Konrad
On Wed, Sep 03, 2025 at 03:37:25PM +0200, Konrad Dybcio wrote: > On 9/3/25 2:37 PM, Abel Vesa wrote: > > On X Elite platform, the eDP PHY uses one more clock called > > refclk. Add it to the schema. > > > > Cc: stable@vger.kernel.org # v6.10 > > Fixes: 5d5607861350 ("dt-bindings: phy: qcom-edp: Add X1E80100 PHY compatibles") > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > > --- > > .../devicetree/bindings/phy/qcom,edp-phy.yaml | 28 +++++++++++++++++++++- > > 1 file changed, 27 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml > > index eb97181cbb9579893b4ee26a39c3559ad87b2fba..a8ba0aa9ff9d83f317bd897a7d564f7e13f6a1e2 100644 > > --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml > > +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml > > @@ -37,12 +37,15 @@ properties: > > - description: PLL register block > > > > clocks: > > - maxItems: 2 > > + minItems: 2 > > + maxItems: 3 > > > > clock-names: > > + minItems: 2 > > items: > > - const: aux > > - const: cfg_ahb > > + - const: refclk > > "ref"? Certainly more consistent with other QCom phy bindings.
On 9/4/25 1:51 AM, Rob Herring wrote: > On Wed, Sep 03, 2025 at 03:37:25PM +0200, Konrad Dybcio wrote: >> On 9/3/25 2:37 PM, Abel Vesa wrote: >>> On X Elite platform, the eDP PHY uses one more clock called >>> refclk. Add it to the schema. >>> >>> Cc: stable@vger.kernel.org # v6.10 >>> Fixes: 5d5607861350 ("dt-bindings: phy: qcom-edp: Add X1E80100 PHY compatibles") >>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> >>> --- >>> .../devicetree/bindings/phy/qcom,edp-phy.yaml | 28 +++++++++++++++++++++- >>> 1 file changed, 27 insertions(+), 1 deletion(-) >>> >>> diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml >>> index eb97181cbb9579893b4ee26a39c3559ad87b2fba..a8ba0aa9ff9d83f317bd897a7d564f7e13f6a1e2 100644 >>> --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml >>> +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml >>> @@ -37,12 +37,15 @@ properties: >>> - description: PLL register block >>> >>> clocks: >>> - maxItems: 2 >>> + minItems: 2 >>> + maxItems: 3 >>> >>> clock-names: >>> + minItems: 2 >>> items: >>> - const: aux >>> - const: cfg_ahb >>> + - const: refclk >> >> "ref"? > > Certainly more consistent with other QCom phy bindings. That, and the name of a clock-names entry ending in 'clk' is simply superfluous Konrad
On 25-09-04 10:11:26, Konrad Dybcio wrote: > On 9/4/25 1:51 AM, Rob Herring wrote: > > On Wed, Sep 03, 2025 at 03:37:25PM +0200, Konrad Dybcio wrote: > >> On 9/3/25 2:37 PM, Abel Vesa wrote: > >>> On X Elite platform, the eDP PHY uses one more clock called > >>> refclk. Add it to the schema. > >>> > >>> Cc: stable@vger.kernel.org # v6.10 > >>> Fixes: 5d5607861350 ("dt-bindings: phy: qcom-edp: Add X1E80100 PHY compatibles") > >>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > >>> --- > >>> .../devicetree/bindings/phy/qcom,edp-phy.yaml | 28 +++++++++++++++++++++- > >>> 1 file changed, 27 insertions(+), 1 deletion(-) > >>> > >>> diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml > >>> index eb97181cbb9579893b4ee26a39c3559ad87b2fba..a8ba0aa9ff9d83f317bd897a7d564f7e13f6a1e2 100644 > >>> --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml > >>> +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml > >>> @@ -37,12 +37,15 @@ properties: > >>> - description: PLL register block > >>> > >>> clocks: > >>> - maxItems: 2 > >>> + minItems: 2 > >>> + maxItems: 3 > >>> > >>> clock-names: > >>> + minItems: 2 > >>> items: > >>> - const: aux > >>> - const: cfg_ahb > >>> + - const: refclk > >> > >> "ref"? > > > > Certainly more consistent with other QCom phy bindings. > > That, and the name of a clock-names entry ending in 'clk' is simply > superfluous Yep. Will fix in v3. Thanks for reviewing.
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