If any of the flag CLK_DIVIDER_ONE_BASED, CLK_DIVIDER_POWER_OF_TWO,
CLK_DIVIDER_MAX_AT_ZERO or CLK_DIVIDER_EVEN_INTEGERS is set, the divider
table will be ignored in _get_div and _get_val. This can lead to subtle
bug when a clock is registered with some flags and an optional table,
with the clock rate and register value being computed with the wrong
type of conversion.

Prevent this by refusing to register a divider with both the flag and
the table set.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/clk/clk-divider.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 8e8f87024e76625f348f1d66c15a7a938fa0c4db..b4861d519bac2121dd015d094c94a5fee2480148 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -561,6 +561,13 @@ struct clk_hw *__clk_hw_register_divider(struct device *dev,
 			return ERR_PTR(-EINVAL);
 		}
 	}
+	if (table && (clk_divider_flags & (CLK_DIVIDER_ONE_BASED |
+					   CLK_DIVIDER_POWER_OF_TWO |
+					   CLK_DIVIDER_MAX_AT_ZERO |
+					   CLK_DIVIDER_EVEN_INTEGERS))) {
+		pr_warn("divider table and flags incompatible\n");
+		return ERR_PTR(-EINVAL);
+	}
 
 	/* allocate the divider */
 	div = kzalloc(sizeof(*div), GFP_KERNEL);

-- 
2.51.0