On Mon, Sep 01, 2025 at 01:59:20PM +0800, Jacky Chou wrote:
> According to PCIe specification, add FMT and TYPE definition
> for TLP header.
>
> Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
> ---
> drivers/pci/pci.h | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> index 34f65d69662e..45d47d6c4f53 100644
> --- a/drivers/pci/pci.h
> +++ b/drivers/pci/pci.h
> @@ -81,6 +81,18 @@ struct pcie_tlp_log;
> #define PCIE_MSG_CODE_DEASSERT_INTC 0x26
> #define PCIE_MSG_CODE_DEASSERT_INTD 0x27
>
> +/* Format of TLP; PCIe r5.0, sec 2.2.1 */
Please update to PCIe r7.0.
> +#define PCIE_TLP_FMT_3DW_NO_DATA 0x00 /* 3DW header, no data */
> +#define PCIE_TLP_FMT_4DW_NO_DATA 0x01 /* 4DW header, no data */
> +#define PCIE_TLP_FMT_3DW_DATA 0x02 /* 3DW header, with data */
> +#define PCIE_TLP_FMT_4DW_DATA 0x03 /* 4DW header, with data */
> +
> +/* Type of TLP; PCIe r5.0, sec 2.2.1 */
> +#define PCIE_TLP_TYPE_CFG0_RD 0x04 /* Config Type 0 Read Request */
> +#define PCIE_TLP_TYPE_CFG0_WR 0x04 /* Config Type 0 Write Request */
> +#define PCIE_TLP_TYPE_CFG1_RD 0x05 /* Config Type 1 Read Request */
> +#define PCIE_TLP_TYPE_CFG1_WR 0x05 /* Config Type 1 Write Request */
> +
> extern const unsigned char pcie_link_speed[];
> extern bool pci_early_dump;
>
> --
> 2.43.0
>