On Fri, Sep 5, 2025 at 11:12 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> On Sun, 31 Aug 2025 01:08:56 +0800
> Chen-Yu Tsai <wens@kernel.org> wrote:
>
> > From: Chen-Yu Tsai <wens@csie.org>
> >
> > When dual-divider clock support was introduced, the P divider offset was
> > left out of the .recalc_rate readback function. This causes the clock
> > rate to become bogus or even zero (possibly due to the P divider being
> > 1, leading to a divide-by-zero).
>
> Ah, a nice catch, thanks for that! Just curious, how did you find this?
> The MMC clocks use the dual divider type as well, but I didn't observe
> them being wrong?
I was looking at clk_summary in debugfs and kept seeing some of the audio
clocks returning 0 and dumped the register to get the actual value. I then
did a printk trace of the .determine_rate callback and saw that one of the
dividers was always 1. I guessed that the .recalc_rate callback was to blame.
> Regardless:
>
> > Fix this by incorporating the P divider offset into the calculation.
> >
> > Fixes: 45717804b75e ("clk: sunxi-ng: mp: introduce dual-divider clock")
> > Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>
> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Thanks!
> Thanks,
> Andre
>
> > ---
> > drivers/clk/sunxi-ng/ccu_mp.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/sunxi-ng/ccu_mp.c b/drivers/clk/sunxi-ng/ccu_mp.c
> > index 354c981943b6..4221b1888b38 100644
> > --- a/drivers/clk/sunxi-ng/ccu_mp.c
> > +++ b/drivers/clk/sunxi-ng/ccu_mp.c
> > @@ -185,7 +185,7 @@ static unsigned long ccu_mp_recalc_rate(struct clk_hw *hw,
> > p &= (1 << cmp->p.width) - 1;
> >
> > if (cmp->common.features & CCU_FEATURE_DUAL_DIV)
> > - rate = (parent_rate / p) / m;
> > + rate = (parent_rate / (p + cmp->p.offset)) / m;
> > else
> > rate = (parent_rate >> p) / m;
> >
>