__pci_bus_size_bridges() goes to great lengths of helping pbus_size_mem()
in which types it should put into a particular bridge window, requiring
passing up to three resource type into pbus_size_mem().
Instead of having complex logic in __pci_bus_size_bridges() and a
non-straightforward interface between those functions, use
pbus_select_window_for_type() and pbus_select_window() to find the correct
bridge window and compare if the resources belong to that window.
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
---
drivers/pci/setup-bus.c | 111 +++++++++-------------------------------
1 file changed, 24 insertions(+), 87 deletions(-)
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index 865bacae9cac..720159bca54d 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -1284,24 +1284,22 @@ static bool pbus_upstream_space_available(struct pci_bus *bus,
* pbus_size_mem() - Size the memory window of a given bus
*
* @bus: The bus
- * @mask: Mask the resource flag, then compare it with type
- * @type: The type of free resource from bridge
- * @type2: Second match type
- * @type3: Third match type
+ * @type: The type of bridge resource
* @min_size: The minimum memory window that must be allocated
* @add_size: Additional optional memory window
* @realloc_head: Track the additional memory window on this list
*
- * Calculate the size of the bus and minimal alignment which guarantees
- * that all child resources fit in this size.
+ * Calculate the size of the bus resource for @type and minimal alignment
+ * which guarantees that all child resources fit in this size.
*
- * Return -ENOSPC if there's no available bus resource of the desired
- * type. Otherwise, set the bus resource start/end to indicate the
- * required size, add things to realloc_head (if supplied), and return 0.
+ * Set the bus resource start/end to indicate the required size if there an
+ * available unassigned bus resource of the desired @type.
+ *
+ * Add optional resource requests to the @realloc_head list if it is
+ * supplied.
*/
-static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
- unsigned long type, unsigned long type2,
- unsigned long type3, resource_size_t min_size,
+static void pbus_size_mem(struct pci_bus *bus, unsigned long type,
+ resource_size_t min_size,
resource_size_t add_size,
struct list_head *realloc_head)
{
@@ -1309,19 +1307,18 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
resource_size_t min_align, win_align, align, size, size0, size1 = 0;
resource_size_t aligns[28]; /* Alignments from 1MB to 128TB */
int order, max_order;
- struct resource *b_res = find_bus_resource_of_type(bus,
- mask | IORESOURCE_PREFETCH, type);
+ struct resource *b_res = pbus_select_window_for_type(bus, type);
resource_size_t children_add_size = 0;
resource_size_t children_add_align = 0;
resource_size_t add_align = 0;
resource_size_t relaxed_align;
if (!b_res)
- return -ENOSPC;
+ return;
/* If resource is already assigned, nothing more to do */
if (b_res->parent)
- return 0;
+ return;
memset(aligns, 0, sizeof(aligns));
max_order = 0;
@@ -1338,11 +1335,9 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
if (!pdev_resources_assignable(dev) ||
!pdev_resource_should_fit(dev, r))
continue;
-
- if ((r->flags & mask) != type &&
- (r->flags & mask) != type2 &&
- (r->flags & mask) != type3)
+ if (b_res != pbus_select_window(bus, r))
continue;
+
r_size = resource_size(r);
/* Put SRIOV requested res to the optional list */
@@ -1428,7 +1423,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
b_res, &bus->busn_res);
b_res->flags |= IORESOURCE_DISABLED;
- return 0;
+ return;
}
resource_set_range(b_res, min_align, size0);
@@ -1441,7 +1436,6 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
(unsigned long long) (size1 - size0),
(unsigned long long) add_align);
}
- return 0;
}
unsigned long pci_cardbus_resource_alignment(struct resource *res)
@@ -1546,12 +1540,11 @@ static void pci_bus_size_cardbus(struct pci_bus *bus,
void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
{
struct pci_dev *dev;
- unsigned long mask, prefmask, type2 = 0, type3 = 0;
resource_size_t additional_io_size = 0, additional_mmio_size = 0,
additional_mmio_pref_size = 0;
struct resource *pref;
struct pci_host_bridge *host;
- int hdr_type, ret;
+ int hdr_type;
list_for_each_entry(dev, &bus->devices, bus_list) {
struct pci_bus *b = dev->subordinate;
@@ -1601,71 +1594,15 @@ void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
additional_io_size, realloc_head);
- /*
- * If there's a 64-bit prefetchable MMIO window, compute
- * the size required to put all 64-bit prefetchable
- * resources in it.
- */
- mask = IORESOURCE_MEM;
- prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
- if (pref && (pref->flags & IORESOURCE_MEM_64)) {
- prefmask |= IORESOURCE_MEM_64;
- ret = pbus_size_mem(bus, prefmask, prefmask,
- prefmask, prefmask,
- realloc_head ? 0 : additional_mmio_pref_size,
- additional_mmio_pref_size, realloc_head);
-
- /*
- * If successful, all non-prefetchable resources
- * and any 32-bit prefetchable resources will go in
- * the non-prefetchable window.
- */
- if (ret == 0) {
- mask = prefmask;
- type2 = prefmask & ~IORESOURCE_MEM_64;
- type3 = prefmask & ~IORESOURCE_PREFETCH;
- }
- }
-
- /*
- * If there is no 64-bit prefetchable window, compute the
- * size required to put all prefetchable resources in the
- * 32-bit prefetchable window (if there is one).
- */
- if (!type2) {
- prefmask &= ~IORESOURCE_MEM_64;
- ret = pbus_size_mem(bus, prefmask, prefmask,
- prefmask, prefmask,
- realloc_head ? 0 : additional_mmio_pref_size,
- additional_mmio_pref_size, realloc_head);
-
- /*
- * If successful, only non-prefetchable resources
- * will go in the non-prefetchable window.
- */
- if (ret == 0)
- mask = prefmask;
- else
- additional_mmio_size += additional_mmio_pref_size;
-
- type2 = type3 = IORESOURCE_MEM;
+ if (pref) {
+ pbus_size_mem(bus,
+ IORESOURCE_MEM | IORESOURCE_PREFETCH |
+ (pref->flags & IORESOURCE_MEM_64),
+ realloc_head ? 0 : additional_mmio_pref_size,
+ additional_mmio_pref_size, realloc_head);
}
- /*
- * Compute the size required to put everything else in the
- * non-prefetchable window. This includes:
- *
- * - all non-prefetchable resources
- * - 32-bit prefetchable resources if there's a 64-bit
- * prefetchable window or no prefetchable window at all
- * - 64-bit prefetchable resources if there's no prefetchable
- * window at all
- *
- * Note that the strategy in __pci_assign_resource() must match
- * that used here. Specifically, we cannot put a 32-bit
- * prefetchable resource in a 64-bit prefetchable window.
- */
- pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3,
+ pbus_size_mem(bus, IORESOURCE_MEM,
realloc_head ? 0 : additional_mmio_size,
additional_mmio_size, realloc_head);
break;
--
2.39.5
On Fri, 2025-08-29 at 16:11 +0300, Ilpo Järvinen wrote: > __pci_bus_size_bridges() goes to great lengths of helping pbus_size_mem() > in which types it should put into a particular bridge window, requiring > passing up to three resource type into pbus_size_mem(). > > Instead of having complex logic in __pci_bus_size_bridges() and a > non-straightforward interface between those functions, use > pbus_select_window_for_type() and pbus_select_window() to find the correct > bridge window and compare if the resources belong to that window. > > Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Hi, this batch became mainline commit ae88d0b9c57f, and causes a warning when booting on my Turris Omnia. Device tree: arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts PCI driver: pci-mvebu Hardware status: The joint mPCIe / mSATA slot carries an mSATA drive, the other two mPCIe slots carry WiFi cards. As far as I can tell, hardware is operating nominally, so the warning looks like a false positive. *** relevant section of the boot log, at ae88d0b9c57f (first bad commit) *** [ 0.024347] mvebu-pcie soc:pcie: host bridge /soc/pcie ranges: [ 0.024372] mvebu-pcie soc:pcie: MEM 0x00f1080000..0x00f1081fff -> 0x0000080000 [ 0.024388] mvebu-pcie soc:pcie: MEM 0x00f1040000..0x00f1041fff -> 0x0000040000 [ 0.024401] mvebu-pcie soc:pcie: MEM 0x00f1044000..0x00f1045fff -> 0x0000044000 [ 0.024414] mvebu-pcie soc:pcie: MEM 0x00f1048000..0x00f1049fff -> 0x0000048000 [ 0.024427] mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0100000000 [ 0.024439] mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0100000000 [ 0.024452] mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0200000000 [ 0.024464] mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0200000000 [ 0.024476] mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0300000000 [ 0.024488] mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0300000000 [ 0.024500] mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0400000000 [ 0.024508] mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0400000000 [ 0.024698] mvebu-pcie soc:pcie: pcie1.0: Slot power limit 10.0W [ 0.024890] mvebu-pcie soc:pcie: pcie2.0: Slot power limit 10.0W [ 0.025099] mvebu-pcie soc:pcie: PCI host bridge to bus 0000:00 [ 0.025107] pci_bus 0000:00: root bus resource [bus 00-ff] [ 0.025114] pci_bus 0000:00: root bus resource [mem 0xf1080000-0xf1081fff] (bus address [0x00080000-0x00081fff]) [ 0.025120] pci_bus 0000:00: root bus resource [mem 0xf1040000-0xf1041fff] (bus address [0x00040000-0x00041fff]) [ 0.025125] pci_bus 0000:00: root bus resource [mem 0xf1044000-0xf1045fff] (bus address [0x00044000-0x00045fff]) [ 0.025135] pci_bus 0000:00: root bus resource [mem 0xf1048000-0xf1049fff] (bus address [0x00048000-0x00049fff]) [ 0.025139] pci_bus 0000:00: root bus resource [mem 0xe0000000-0xe7ffffff] [ 0.025143] pci_bus 0000:00: root bus resource [io 0x1000-0xeffff] [ 0.025262] pci 0000:00:02.0: [11ab:6820] type 01 class 0x060400 PCIe Root Port [ 0.025277] pci 0000:00:02.0: PCI bridge to [bus 00] [ 0.025284] pci 0000:00:02.0: bridge window [io 0x0000-0x0fff] [ 0.025289] pci 0000:00:02.0: bridge window [mem 0x00000000-0x000fffff] [ 0.025484] /soc/pcie/pcie@2,0: Fixed dependency cycle(s) with /soc/pcie/pcie@2,0/interrupt-controller [ 0.025524] pci 0000:00:03.0: [11ab:6820] type 01 class 0x060400 PCIe Root Port [ 0.025537] pci 0000:00:03.0: PCI bridge to [bus 00] [ 0.025543] pci 0000:00:03.0: bridge window [io 0x0000-0x0fff] [ 0.025547] pci 0000:00:03.0: bridge window [mem 0x00000000-0x000fffff] [ 0.025665] /soc/pcie/pcie@3,0: Fixed dependency cycle(s) with /soc/pcie/pcie@3,0/interrupt-controller [ 0.026453] PCI: bus0: Fast back to back transfers disabled [ 0.026459] pci 0000:00:02.0: bridge configuration invalid ([bus 00-00]), reconfiguring [ 0.026466] pci 0000:00:03.0: bridge configuration invalid ([bus 00-00]), reconfiguring [ 0.026538] pci 0000:01:00.0: [168c:002e] type 00 class 0x028000 PCIe Legacy Endpoint [ 0.026577] pci 0000:01:00.0: BAR 0 [mem 0xc0000000-0xc000ffff 64bit] [ 0.026669] pci 0000:01:00.0: supports D1 [ 0.026673] pci 0000:01:00.0: PME# supported from D0 D1 D3hot [ 0.026783] PCI: bus1: Fast back to back transfers disabled [ 0.026788] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01 [ 0.026860] pci 0000:02:00.0: [168c:003c] type 00 class 0x028000 PCIe Endpoint [ 0.026898] pci 0000:02:00.0: BAR 0 [mem 0xc8000000-0xc81fffff 64bit] [ 0.026909] pci 0000:02:00.0: ROM [mem 0xc8200000-0xc820ffff pref] [ 0.026987] pci 0000:02:00.0: supports D1 D2 [ 0.027083] PCI: bus2: Fast back to back transfers disabled [ 0.027088] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to 02 [ 0.027107] pci 0000:00:03.0: bridge window [mem 0x00200000-0x003fffff] to [bus 02] add_size 200000 add_align 200000 [ 0.027115] pci 0000:00:03.0: bridge window [mem 0x00200000-0x003fffff] to [bus 02] add_size 200000 add_align 200000 [ 0.027131] pci 0000:00:03.0: bridge window [mem 0xe0000000-0xe03fffff]: assigned [ 0.027138] pci 0000:00:02.0: bridge window [mem 0xe0400000-0xe04fffff]: assigned [ 0.027146] pci 0000:01:00.0: BAR 0 [mem 0xe0400000-0xe040ffff 64bit]: assigned [ 0.027158] pci 0000:00:02.0: PCI bridge to [bus 01] [ 0.027165] pci 0000:00:02.0: bridge window [mem 0xe0400000-0xe04fffff] [ 0.027178] pci 0000:02:00.0: BAR 0 [mem 0xe0000000-0xe01fffff 64bit]: assigned [ 0.027188] pci 0000:02:00.0: ROM [mem 0xe0200000-0xe020ffff pref]: assigned [ 0.027194] pci 0000:00:03.0: PCI bridge to [bus 02] [ 0.027199] pci 0000:00:03.0: bridge window [mem 0xe0000000-0xe03fffff] [ 0.027208] ------------[ cut here ]------------ [ 0.027211] WARNING: CPU: 0 PID: 1 at drivers/pci/setup-bus.c:2373 pci_assign_unassigned_root_bus_resources+0x1bc/0x234 [ 0.027230] Modules linked in: [ 0.027238] CPU: 0 UID: 0 PID: 1 Comm: swapper/0 Not tainted 6.17.0-rc1+ #49 NONE [ 0.027246] Hardware name: Marvell Armada 380/385 (Device Tree) [ 0.027250] Call trace: [ 0.027258] unwind_backtrace from show_stack+0x10/0x14 [ 0.027278] show_stack from dump_stack_lvl+0x50/0x64 [ 0.027288] dump_stack_lvl from __warn+0x7c/0xd4 [ 0.027301] __warn from warn_slowpath_fmt+0x158/0x15c [ 0.027314] warn_slowpath_fmt from pci_assign_unassigned_root_bus_resources+0x1bc/0x234 [ 0.027328] pci_assign_unassigned_root_bus_resources from pci_host_probe+0x50/0xb8 [ 0.027341] pci_host_probe from platform_probe+0x48/0x84 [ 0.027351] platform_probe from really_probe+0xc8/0x2c8 [ 0.027364] really_probe from driver_probe_device+0x38/0x114 [ 0.027378] driver_probe_device from __driver_attach+0x9c/0x194 [ 0.027391] __driver_attach from bus_for_each_dev+0x60/0x94 [ 0.027404] bus_for_each_dev from bus_add_driver+0xc8/0x1e8 [ 0.027417] bus_add_driver from driver_register+0x84/0x138 [ 0.027426] driver_register from do_one_initcall+0x44/0x268 [ 0.027433] do_one_initcall from kernel_init_freeable+0x258/0x2c8 [ 0.027445] kernel_init_freeable from kernel_init+0x1c/0x130 [ 0.027458] kernel_init from ret_from_fork+0x14/0x28 [ 0.027466] Exception stack(0xf0831fb0 to 0xf0831ff8) [ 0.027472] 1fa0: 00000000 00000000 00000000 00000000 [ 0.027477] 1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 [ 0.027481] 1fe0: 00000000 00000000 00000000 00000000 00000013 00000000 [ 0.027485] ---[ end trace 0000000000000000 ]--- [ 0.027489] pci_bus 0000:00: resource 4 [mem 0xf1080000-0xf1081fff] [ 0.027495] pci_bus 0000:00: resource 5 [mem 0xf1040000-0xf1041fff] [ 0.027500] pci_bus 0000:00: resource 6 [mem 0xf1044000-0xf1045fff] [ 0.027504] pci_bus 0000:00: resource 7 [mem 0xf1048000-0xf1049fff] [ 0.027508] pci_bus 0000:00: resource 8 [mem 0xe0000000-0xe7ffffff] [ 0.027512] pci_bus 0000:00: resource 9 [io 0x1000-0xeffff] [ 0.027517] pci_bus 0000:01: resource 1 [mem 0xe0400000-0xe04fffff] [ 0.027522] pci_bus 0000:02: resource 1 [mem 0xe0000000-0xe03fffff] *** relevant section of the boot log, at 13016e15d595 (last good commit) *** [ 0.024666] mvebu-pcie soc:pcie: host bridge /soc/pcie ranges: [ 0.024690] mvebu-pcie soc:pcie: MEM 0x00f1080000..0x00f1081fff -> 0x0000080000 [ 0.024706] mvebu-pcie soc:pcie: MEM 0x00f1040000..0x00f1041fff -> 0x0000040000 [ 0.024719] mvebu-pcie soc:pcie: MEM 0x00f1044000..0x00f1045fff -> 0x0000044000 [ 0.024732] mvebu-pcie soc:pcie: MEM 0x00f1048000..0x00f1049fff -> 0x0000048000 [ 0.024745] mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0100000000 [ 0.024757] mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0100000000 [ 0.024770] mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0200000000 [ 0.024782] mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0200000000 [ 0.024794] mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0300000000 [ 0.024806] mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0300000000 [ 0.024818] mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0400000000 [ 0.024827] mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0400000000 [ 0.025022] mvebu-pcie soc:pcie: pcie1.0: Slot power limit 10.0W [ 0.025210] mvebu-pcie soc:pcie: pcie2.0: Slot power limit 10.0W [ 0.025451] mvebu-pcie soc:pcie: PCI host bridge to bus 0000:00 [ 0.025459] pci_bus 0000:00: root bus resource [bus 00-ff] [ 0.025466] pci_bus 0000:00: root bus resource [mem 0xf1080000-0xf1081fff] (bus address [0x00080000-0x00081fff]) [ 0.025472] pci_bus 0000:00: root bus resource [mem 0xf1040000-0xf1041fff] (bus address [0x00040000-0x00041fff]) [ 0.025477] pci_bus 0000:00: root bus resource [mem 0xf1044000-0xf1045fff] (bus address [0x00044000-0x00045fff]) [ 0.025482] pci_bus 0000:00: root bus resource [mem 0xf1048000-0xf1049fff] (bus address [0x00048000-0x00049fff]) [ 0.025487] pci_bus 0000:00: root bus resource [mem 0xe0000000-0xe7ffffff] [ 0.025491] pci_bus 0000:00: root bus resource [io 0x1000-0xeffff] [ 0.025617] pci 0000:00:02.0: [11ab:6820] type 01 class 0x060400 PCIe Root Port [ 0.025633] pci 0000:00:02.0: PCI bridge to [bus 00] [ 0.025639] pci 0000:00:02.0: bridge window [io 0x0000-0x0fff] [ 0.025644] pci 0000:00:02.0: bridge window [mem 0x00000000-0x000fffff] [ 0.025794] /soc/pcie/pcie@2,0: Fixed dependency cycle(s) with /soc/pcie/pcie@2,0/interrupt-controller [ 0.025832] pci 0000:00:03.0: [11ab:6820] type 01 class 0x060400 PCIe Root Port [ 0.025844] pci 0000:00:03.0: PCI bridge to [bus 00] [ 0.025851] pci 0000:00:03.0: bridge window [io 0x0000-0x0fff] [ 0.025855] pci 0000:00:03.0: bridge window [mem 0x00000000-0x000fffff] [ 0.025968] /soc/pcie/pcie@3,0: Fixed dependency cycle(s) with /soc/pcie/pcie@3,0/interrupt-controller [ 0.026757] PCI: bus0: Fast back to back transfers disabled [ 0.026762] pci 0000:00:02.0: bridge configuration invalid ([bus 00-00]), reconfiguring [ 0.026769] pci 0000:00:03.0: bridge configuration invalid ([bus 00-00]), reconfiguring [ 0.026845] pci 0000:01:00.0: [168c:002e] type 00 class 0x028000 PCIe Legacy Endpoint [ 0.026884] pci 0000:01:00.0: BAR 0 [mem 0xc0000000-0xc000ffff 64bit] [ 0.026976] pci 0000:01:00.0: supports D1 [ 0.026980] pci 0000:01:00.0: PME# supported from D0 D1 D3hot [ 0.027082] PCI: bus1: Fast back to back transfers disabled [ 0.027087] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01 [ 0.027163] pci 0000:02:00.0: [168c:003c] type 00 class 0x028000 PCIe Endpoint [ 0.027201] pci 0000:02:00.0: BAR 0 [mem 0xc8000000-0xc81fffff 64bit] [ 0.027212] pci 0000:02:00.0: ROM [mem 0xc8200000-0xc820ffff pref] [ 0.027290] pci 0000:02:00.0: supports D1 D2 [ 0.027381] PCI: bus2: Fast back to back transfers disabled [ 0.027386] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to 02 [ 0.027405] pci 0000:00:03.0: bridge window [mem 0x00200000-0x003fffff] to [bus 02] add_size 200000 add_align 200000 [ 0.027423] pci 0000:00:03.0: bridge window [mem 0xe0000000-0xe03fffff]: assigned [ 0.027430] pci 0000:00:02.0: bridge window [mem 0xe0400000-0xe04fffff]: assigned [ 0.027438] pci 0000:01:00.0: BAR 0 [mem 0xe0400000-0xe040ffff 64bit]: assigned [ 0.027450] pci 0000:00:02.0: PCI bridge to [bus 01] [ 0.027457] pci 0000:00:02.0: bridge window [mem 0xe0400000-0xe04fffff] [ 0.027470] pci 0000:02:00.0: BAR 0 [mem 0xe0000000-0xe01fffff 64bit]: assigned [ 0.027481] pci 0000:02:00.0: ROM [mem 0xe0200000-0xe020ffff pref]: assigned [ 0.027487] pci 0000:00:03.0: PCI bridge to [bus 02] [ 0.027492] pci 0000:00:03.0: bridge window [mem 0xe0000000-0xe03fffff] [ 0.027502] pci_bus 0000:00: resource 4 [mem 0xf1080000-0xf1081fff] [ 0.027507] pci_bus 0000:00: resource 5 [mem 0xf1040000-0xf1041fff] [ 0.027511] pci_bus 0000:00: resource 6 [mem 0xf1044000-0xf1045fff] [ 0.027515] pci_bus 0000:00: resource 7 [mem 0xf1048000-0xf1049fff] [ 0.027519] pci_bus 0000:00: resource 8 [mem 0xe0000000-0xe7ffffff] [ 0.027523] pci_bus 0000:00: resource 9 [io 0x1000-0xeffff] [ 0.027528] pci_bus 0000:01: resource 1 [mem 0xe0400000-0xe04fffff] [ 0.027532] pci_bus 0000:02: resource 1 [mem 0xe0000000-0xe03fffff] #regzbot introduced: ae88d0b9c57f Thanks, Klaus
On Sat, 2025-10-18 at 10:14 +0200, Klaus Kudielka wrote: [...] > Device tree: arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts > PCI driver: pci-mvebu > Hardware status: The joint mPCIe / mSATA slot carries an mSATA drive, the other > two mPCIe slots carry WiFi cards. > > As far as I can tell, hardware is operating nominally, so the warning looks like > a false positive. In the meantime, I stared a bit at the logs, and at the code. WITH the offending commit, I see TWO identical lines before the WARNING: > [ 0.027107] pci 0000:00:03.0: bridge window [mem 0x00200000-0x003fffff] to [bus 02] add_size 200000 add_align 200000 > [ 0.027115] pci 0000:00:03.0: bridge window [mem 0x00200000-0x003fffff] to [bus 02] add_size 200000 add_align 200000 So, this part of pbus_size_mem() now seems to be called *TWICE* for the same bridge window: add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align); pci_info(bus->self, "bridge window %pR to %pR add_size %llx add_align %llx\n", b_res, &bus->busn_res, (unsigned long long) (size1 - size0), (unsigned long long) add_align); WITHOUT the offending commit, I see only one line, and no WARNING. > [ 0.027405] pci 0000:00:03.0: bridge window [mem 0x00200000-0x003fffff] to [bus 02] add_size 200000 add_align 200000 This behavior change really looks suspicious to me (maybe resulting in two identical entries in the realloc_list). Does that ring any bell? Thanks, Klaus
On Sat, 2025-10-25 at 12:11 +0200, Klaus Kudielka wrote:
>
> > [ 0.027107] pci 0000:00:03.0: bridge window [mem 0x00200000-0x003fffff] to [bus 02] add_size 200000 add_align 200000
> > [ 0.027115] pci 0000:00:03.0: bridge window [mem 0x00200000-0x003fffff] to [bus 02] add_size 200000 add_align 200000
>
> So, this part of pbus_size_mem() now seems to be called *TWICE* for the same bridge window:
>
> add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align);
> pci_info(bus->self, "bridge window %pR to %pR add_size %llx add_align %llx\n",
> b_res, &bus->busn_res,
> (unsigned long long) (size1 - size0),
> (unsigned long long) add_align);
>
>
>
> WITHOUT the offending commit, I see only one line, and no WARNING.
> > [ 0.027405] pci 0000:00:03.0: bridge window [mem 0x00200000-0x003fffff] to [bus 02] add_size 200000 add_align 200000
>
>
After some more testing, I think I know what is going on.
- My device seems to have only non-prefetchable IO resources.
- In pci_bus_size_bridges(), pbus_size_mem() is called twice, once with IORESOURCE_PREFETCH, once without.
- This seems to be the intended behaviour (with or without the offending commit).
- What DOES make the difference, is the use of pbus_select_window_for_type() inside pbus_size_mem().
- On my device, that function returns the ***non-prefetchable*** resource, even if being asked for a prefetchable one.
- End result: b_res is valid (and identical) in both calls to pbus_size_mem().
- Honestly, that does not look right to me.
Indeed, my device goes back to the original behaviour (without WARNING), if I go back to the original use of
find_bus_resource_of_type():
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -1312,7 +1312,9 @@ static void pbus_size_mem(struct pci_bus *bus, unsigned long type,
resource_size_t min_align, win_align, align, size, size0, size1 = 0;
resource_size_t aligns[28]; /* Alignments from 1MB to 128TB */
int order, max_order;
- struct resource *b_res = pbus_select_window_for_type(bus, type);
+ struct resource *b_res = find_bus_resource_of_type(bus,
+ IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
+ type);
resource_size_t children_add_size = 0;
resource_size_t children_add_align = 0;
resource_size_t add_align = 0;
Comments?
On Sat, 25 Oct 2025, Klaus Kudielka wrote: > On Sat, 2025-10-25 at 12:11 +0200, Klaus Kudielka wrote: > > > > > [ 0.027107] pci 0000:00:03.0: bridge window [mem 0x00200000-0x003fffff] to [bus 02] add_size 200000 add_align 200000 > > > [ 0.027115] pci 0000:00:03.0: bridge window [mem 0x00200000-0x003fffff] to [bus 02] add_size 200000 add_align 200000 > > > > So, this part of pbus_size_mem() now seems to be called *TWICE* for the same bridge window: > > > > add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align); > > pci_info(bus->self, "bridge window %pR to %pR add_size %llx add_align %llx\n", > > b_res, &bus->busn_res, > > (unsigned long long) (size1 - size0), > > (unsigned long long) add_align); > > > > > > > > WITHOUT the offending commit, I see only one line, and no WARNING. > > > [ 0.027405] pci 0000:00:03.0: bridge window [mem 0x00200000-0x003fffff] to [bus 02] add_size 200000 add_align 200000 > > > > > > > After some more testing, I think I know what is going on. > > - My device seems to have only non-prefetchable IO resources. > - In pci_bus_size_bridges(), pbus_size_mem() is called twice, once with IORESOURCE_PREFETCH, once without. > - This seems to be the intended behaviour (with or without the offending commit). > > - What DOES make the difference, is the use of pbus_select_window_for_type() inside pbus_size_mem(). > - On my device, that function returns the ***non-prefetchable*** resource, even if being asked for a prefetchable one. > - End result: b_res is valid (and identical) in both calls to pbus_size_mem(). > - Honestly, that does not look right to me. > > > Indeed, my device goes back to the original behaviour (without WARNING), if I go back to the original use of > find_bus_resource_of_type(): > > > --- a/drivers/pci/setup-bus.c > +++ b/drivers/pci/setup-bus.c > @@ -1312,7 +1312,9 @@ static void pbus_size_mem(struct pci_bus *bus, unsigned long type, > resource_size_t min_align, win_align, align, size, size0, size1 = 0; > resource_size_t aligns[28]; /* Alignments from 1MB to 128TB */ > int order, max_order; > - struct resource *b_res = pbus_select_window_for_type(bus, type); > + struct resource *b_res = find_bus_resource_of_type(bus, > + IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_MEM_64, > + type); > resource_size_t children_add_size = 0; > resource_size_t children_add_align = 0; > resource_size_t add_align = 0; > > > > Comments? Hi Klaus, I'm sorry this ended up falling through cracks until now (this is far from the only regression I've on my table at the moment). Big kudos for you from figuring out what went wrong! For a bridge which doesn't have a prefetchable window, pbus_size_mem() should not be called for it. I've sent a fix patch separately. Please test it. -- i.
© 2016 - 2026 Red Hat, Inc.