The values are written to ASN_HASH[0..2] registers. The property is
called "l2-hash-values" in the downstream driver.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
---
 .../devicetree/bindings/gpu/arm,mali-valhall-csf.yaml     | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
index a5b4e00217587..258bcba66d1d1 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
@@ -85,6 +85,14 @@ properties:
 
   dma-coherent: true
 
+  asn-hash:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description:
+      The values are written to ASN_HASH[0..2] registers. They affect how
+      physical addresses are mapped to L2 cache slices.
+    minItems: 3
+    maxItems: 3
+
 required:
   - compatible
   - reg
-- 
2.51.0.318.gd7df087d1a-goog

On 28/08/2025 22:18, Chia-I Wu wrote:
> The values are written to ASN_HASH[0..2] registers. The property is
> called "l2-hash-values" in the downstream driver.

We don't add properties based on downstream drivers. Please provide some
sort of rationale, including explanation why this is not SoC/compatible
specific.

> 
> Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
> ---
>  .../devicetree/bindings/gpu/arm,mali-valhall-csf.yaml     | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
> index a5b4e00217587..258bcba66d1d1 100644
> --- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
> @@ -85,6 +85,14 @@ properties:
>  
>    dma-coherent: true
>  
> +  asn-hash:

Missing vendor prefix or please explain which common schema has it
already defined.


Best regards,
Krzysztof

On Thu, 28 Aug 2025 13:18:05 -0700
Chia-I Wu <olvaffe@gmail.com> wrote:

> The values are written to ASN_HASH[0..2] registers. The property is
> called "l2-hash-values" in the downstream driver.
> 
> Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
> ---
>  .../devicetree/bindings/gpu/arm,mali-valhall-csf.yaml     | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
> index a5b4e00217587..258bcba66d1d1 100644
> --- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
> @@ -85,6 +85,14 @@ properties:
>  
>    dma-coherent: true
>  
> +  asn-hash:
> +    $ref: /schemas/types.yaml#/definitions/uint32-array
> +    description:
> +      The values are written to ASN_HASH[0..2] registers. They affect how
> +      physical addresses are mapped to L2 cache slices.

If this is per-SoC integration details, I would hide that behind the
compatible string and have some panthor_soc_data attached to the
of_device_id entries.

> +    minItems: 3
> +    maxItems: 3
> +
>  required:
>    - compatible
>    - reg