The Tesla FSD CSIS link controller is used to configure MIPI CSI-2
Rx link operations.
The Tesla FSD SoC include a MIPI CSI-2 Rx IP core named CSIS, which is
compatible with the CSIS IP found in NXP i.MX7 and i.MX8 SoCs. Add the
compatible string "tesla,fsd-mipi-csi2" to support the MIPI CSI-2 Rx
link operation on the Tesla FSD SoC.
Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
---
.../bindings/media/nxp,imx-mipi-csi2.yaml | 91 +++++++++++++++----
1 file changed, 71 insertions(+), 20 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml
index 41ad5b84eaeb..39b9447fd40c 100644
--- a/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml
+++ b/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml
@@ -14,7 +14,7 @@ description: |-
The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
receiver IP core named CSIS. The IP core originates from Samsung, and may be
compatible with some of the Exynos4 and S5P SoCs. i.MX7 SoCs use CSIS version
- 3.3, and i.MX8 SoCs use CSIS version 3.6.3.
+ 3.3, i.MX8 SoCs use CSIS version 3.6.3 and FSD SoC uses CSIS version 4.3.
While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
completely wrapped by the CSIS and doesn't expose a control interface of its
@@ -26,6 +26,7 @@ properties:
- enum:
- fsl,imx7-mipi-csi2
- fsl,imx8mm-mipi-csi2
+ - tesla,fsd-mipi-csi2
- items:
- enum:
- fsl,imx8mp-mipi-csi2
@@ -38,24 +39,21 @@ properties:
maxItems: 1
clocks:
- minItems: 3
- items:
- - description: The peripheral clock (a.k.a. APB clock)
- - description: The external clock (optionally used as the pixel clock)
- - description: The MIPI D-PHY clock
- - description: The AXI clock
+ minItems: 2
+ maxItems: 4
clock-names:
- minItems: 3
- items:
- - const: pclk
- - const: wrap
- - const: phy
- - const: axi
+ minItems: 2
+ maxItems: 4
power-domains:
maxItems: 1
+ tesla,syscon-csis:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ Syscon used to hold and release the reset of MIPI D-PHY
+
phy-supply:
description: The MIPI D-PHY digital power supply
@@ -93,7 +91,8 @@ properties:
properties:
data-lanes:
description:
- Note that 'fsl,imx7-mipi-csi2' only supports up to 2 data lines.
+ Note that 'fsl,imx7-mipi-csi2' only supports up to 2 data
+ lines.
minItems: 1
items:
- const: 1
@@ -115,7 +114,6 @@ required:
- interrupts
- clocks
- clock-names
- - power-domains
- ports
additionalProperties: false
@@ -124,20 +122,73 @@ allOf:
- if:
properties:
compatible:
- contains:
- const: fsl,imx7-mipi-csi2
+ const: fsl,imx7-mipi-csi2
then:
+ properties:
+ clocks:
+ items:
+ - description: The peripheral clock (a.k.a. APB clock)
+ - description: The external clock (optionally used as the pixel
+ clock)
+ - description: The MIPI D-PHY clock
+ clock-names:
+ items:
+ - const: pclk
+ - const: wrap
+ - const: phy
+ tesla,syscon-csis: false
+ fsl,num-channels: false
required:
+ - power-domains
- phy-supply
- resets
- else:
+
+ - if:
+ properties:
+ compatible:
+ const: fsl,imx8mm-mipi-csi2
+ then:
properties:
clocks:
- minItems: 4
+ items:
+ - description: The peripheral clock (a.k.a. APB clock)
+ - description: The external clock (optionally used as the pixel
+ clock)
+ - description: The MIPI D-PHY clock
+ - description: The AXI clock
clock-names:
- minItems: 4
+ items:
+ - const: pclk
+ - const: wrap
+ - const: phy
+ - const: axi
+ tesla,syscon-csis: false
+ fsl,num-channels: false
phy-supply: false
resets: false
+ required:
+ - power-domains
+
+ - if:
+ properties:
+ compatible:
+ const: tesla,fsd-mipi-csi2
+ then:
+ properties:
+ clocks:
+ items:
+ - description: The peripheral clock (a.k.a. APB clock)
+ - description: The DMA clock
+ clocks-names:
+ items:
+ - const: pclk
+ - const: aclk
+ phy-supply: false
+ resets: false
+ power-domains: false
+ required:
+ - tesla,syscon-csis
+ - fsl,num-channels
examples:
- |
--
2.49.0On Thu, Aug 28, 2025 at 02:29:05PM +0530, Inbaraj E wrote: > The Tesla FSD CSIS link controller is used to configure MIPI CSI-2 > Rx link operations. > > The Tesla FSD SoC include a MIPI CSI-2 Rx IP core named CSIS, which is > compatible with the CSIS IP found in NXP i.MX7 and i.MX8 SoCs. Add the > compatible string "tesla,fsd-mipi-csi2" to support the MIPI CSI-2 Rx > link operation on the Tesla FSD SoC. > > Signed-off-by: Inbaraj E <inbaraj.e@samsung.com> > --- > .../bindings/media/nxp,imx-mipi-csi2.yaml | 91 +++++++++++++++---- > 1 file changed, 71 insertions(+), 20 deletions(-) > > diff --git a/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml > index 41ad5b84eaeb..39b9447fd40c 100644 > --- a/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml > +++ b/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml > @@ -14,7 +14,7 @@ description: |- > The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2 > receiver IP core named CSIS. The IP core originates from Samsung, and may be > compatible with some of the Exynos4 and S5P SoCs. i.MX7 SoCs use CSIS version > - 3.3, and i.MX8 SoCs use CSIS version 3.6.3. > + 3.3, i.MX8 SoCs use CSIS version 3.6.3 and FSD SoC uses CSIS version 4.3. > > While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is > completely wrapped by the CSIS and doesn't expose a control interface of its > @@ -26,6 +26,7 @@ properties: > - enum: > - fsl,imx7-mipi-csi2 > - fsl,imx8mm-mipi-csi2 > + - tesla,fsd-mipi-csi2 > - items: > - enum: > - fsl,imx8mp-mipi-csi2 > @@ -38,24 +39,21 @@ properties: > maxItems: 1 > > clocks: > - minItems: 3 > - items: > - - description: The peripheral clock (a.k.a. APB clock) > - - description: The external clock (optionally used as the pixel clock) > - - description: The MIPI D-PHY clock > - - description: The AXI clock > + minItems: 2 > + maxItems: 4 > > clock-names: > - minItems: 3 > - items: > - - const: pclk > - - const: wrap > - - const: phy > - - const: axi > + minItems: 2 > + maxItems: 4 > > power-domains: > maxItems: 1 > > + tesla,syscon-csis: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: > + Syscon used to hold and release the reset of MIPI D-PHY Reset? Sounds like you should be using the reset binding. > + > phy-supply: > description: The MIPI D-PHY digital power supply > > @@ -93,7 +91,8 @@ properties: > properties: > data-lanes: > description: > - Note that 'fsl,imx7-mipi-csi2' only supports up to 2 data lines. > + Note that 'fsl,imx7-mipi-csi2' only supports up to 2 data > + lines. Reformatting should be a separate patch. > minItems: 1 > items: > - const: 1 > @@ -115,7 +114,6 @@ required: > - interrupts > - clocks > - clock-names > - - power-domains > - ports > > additionalProperties: false > @@ -124,20 +122,73 @@ allOf: > - if: > properties: > compatible: > - contains: > - const: fsl,imx7-mipi-csi2 > + const: fsl,imx7-mipi-csi2 'contains' was correct. It is more future proof when there is another SoC that is backwards compatible with imx7. > then: > + properties: > + clocks: > + items: > + - description: The peripheral clock (a.k.a. APB clock) > + - description: The external clock (optionally used as the pixel > + clock) > + - description: The MIPI D-PHY clock > + clock-names: > + items: > + - const: pclk > + - const: wrap > + - const: phy > + tesla,syscon-csis: false > + fsl,num-channels: false blank line > required: > + - power-domains > - phy-supply > - resets > - else: > + > + - if: > + properties: > + compatible: > + const: fsl,imx8mm-mipi-csi2 > + then: > properties: > clocks: > - minItems: 4 > + items: > + - description: The peripheral clock (a.k.a. APB clock) > + - description: The external clock (optionally used as the pixel > + clock) > + - description: The MIPI D-PHY clock > + - description: The AXI clock > clock-names: > - minItems: 4 > + items: > + - const: pclk > + - const: wrap > + - const: phy > + - const: axi > + tesla,syscon-csis: false > + fsl,num-channels: false > phy-supply: false > resets: false blank line > + required: > + - power-domains > + > + - if: > + properties: > + compatible: > + const: tesla,fsd-mipi-csi2 > + then: > + properties: > + clocks: > + items: > + - description: The peripheral clock (a.k.a. APB clock) > + - description: The DMA clock Wouldn't this be the same as the "AXI clock"? > + clocks-names: > + items: > + - const: pclk > + - const: aclk > + phy-supply: false > + resets: false > + power-domains: false blank line > + required: > + - tesla,syscon-csis > + - fsl,num-channels > > examples: > - | > -- > 2.49.0 >
Hi Rob, Thanks for the review > > + description: > > + Syscon used to hold and release the reset of MIPI D-PHY > > Reset? Sounds like you should be using the reset binding. The Tesla FSD Soc does not have a dedicated reset controller. Instead, we are using the system controller which is MMIO Space handled by syscon driver, to assert or de-assert the D-PHY reset. So, I prefer to use syscon. > > > + > > phy-supply: > > description: The MIPI D-PHY digital power supply > > > > @@ -93,7 +91,8 @@ properties: > > properties: > > data-lanes: > > description: > > - Note that 'fsl,imx7-mipi-csi2' only supports up to 2 data lines. > > + Note that 'fsl,imx7-mipi-csi2' only supports up to 2 data > > + lines. > > Reformatting should be a separate patch. Sure, I'll add new patch in next patchset. > > > minItems: 1 > > items: > > - const: 1 > > @@ -115,7 +114,6 @@ required: > > - interrupts > > - clocks > > - clock-names > > - - power-domains > > - ports > > > > additionalProperties: false > > @@ -124,20 +122,73 @@ allOf: > > - if: > > properties: > > compatible: > > - contains: > > - const: fsl,imx7-mipi-csi2 > > + const: fsl,imx7-mipi-csi2 > > 'contains' was correct. It is more future proof when there is another SoC that > is backwards compatible with imx7. Sure, I'll add new patch in next patchset. > > > then: > > + properties: > > + clocks: > > + items: > > + - description: The peripheral clock (a.k.a. APB clock) > > + - description: The external clock (optionally used as the pixel > > + clock) > > + - description: The MIPI D-PHY clock > > + clock-names: > > + items: > > + - const: pclk > > + - const: wrap > > + - const: phy > > + tesla,syscon-csis: false > > + fsl,num-channels: false > > blank line Will remove in nextpatchset. > > > required: > > + - power-domains > > - phy-supply > > - resets > > - else: > > + > > + - if: > > + properties: > > + compatible: > > + const: fsl,imx8mm-mipi-csi2 > > + then: > > properties: > > clocks: > > - minItems: 4 > > + items: > > + - description: The peripheral clock (a.k.a. APB clock) > > + - description: The external clock (optionally used as the pixel > > + clock) > > + - description: The MIPI D-PHY clock > > + - description: The AXI clock > > clock-names: > > - minItems: 4 > > + items: > > + - const: pclk > > + - const: wrap > > + - const: phy > > + - const: axi > > + tesla,syscon-csis: false > > + fsl,num-channels: false > > phy-supply: false > > resets: false > > blank line > > > + required: > > + - power-domains > > + > > + - if: > > + properties: > > + compatible: > > + const: tesla,fsd-mipi-csi2 > > + then: > > + properties: > > + clocks: > > + items: > > + - description: The peripheral clock (a.k.a. APB clock) > > + - description: The DMA clock > > Wouldn't this be the same as the "AXI clock"? According to v4.3 manual it is DMA clock. > > > + clocks-names: > > + items: > > + - const: pclk > > + - const: aclk > > + phy-supply: false > > + resets: false > > + power-domains: false > > blank line Sure will remove in next patchset. > > > + required: > > + - tesla,syscon-csis > > + - fsl,num-channels > > > > examples: > > - | > > -- > > 2.49.0 > > Regards, Inbaraj E
On 17/09/2025 21:09, Inbaraj E wrote: > Hi Rob, > > Thanks for the review > > >>> + description: >>> + Syscon used to hold and release the reset of MIPI D-PHY >> >> Reset? Sounds like you should be using the reset binding. > > The Tesla FSD Soc does not have a dedicated reset controller. Instead, we > are using the > system controller which is MMIO Space handled by syscon driver, to assert or > de-assert the D-PHY But that's the reset controller, no? Best regards, Krzysztof
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